607 results about "Address control" patented technology

This provides for controlling mobile device functions and features. For example, it limits or disables the use of some of mobile device features which could cause distraction to the user, when the user is engaged in another activity. In an example, it enables other mobile device features based on occurrence of events related to the user or environment. Another example addresses controlling the mobile device features, such as SMS, while the user is in a vehicle or driving. Another example restricts the ability of the driver of a vehicle to text, while the vehicle is in motion, by automatically disabling the texting ability of mobile device within and around the perimeter of the driver's seat. Other variations, examples, improvements, detection mechanisms, models, techniques, calculations, verification mechanisms, and features are also described in details.

A system and method for a wireless device to efficiently access affiliated addresses across linked topical communities, such as an Internet WebRing, through a wireless gateway. The invention includes a processing unit running on a wireless device controlled by an affiliated address control program. The processing unit includes a processing unit with a subject processor, a program store for holding an apparatus control program, a network address sub-processor, an address array referrer, an input mechanism, a display device for selecting retrieved affiliated addresses, and a high speed memory for holding site address selectors and associated content buffer. The wireless device communicates with a network via conventional wireless communication means which provides a path for updating the content buffer and array referrer, as well as transference of other types of sensory data. Means for predicting search failures is also integrated into the apparatus control program of the processing unit. Data received from the wireless gateway is statistically preprocessed then supplied to a processor called a network address sub-processor. The system then incorporates sorted affiliated addresses into the system on the wireless device to make possible a real-time detector system for a wireless device accessing content through a wireless gateway. The system may be offered as a service benefit for wireless device subscription or as a per occurrence chargeable item for a wireless subscriber. The system relieves the standard “hit-or-miss” method for affiliated address selection and site address storage and retrieval.

A single chip microcomputer comprises a central processing unit (CPU) 2, a on-chip RAM 3, a on-chip ROM 5, a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU 2 with the RAM 3 and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU 2 with the RAM 3 and passing address data corresponding to the data passed through the third bus SDBUS. The CPU 2 has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM 3 where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS. The RAM 3 has a memory cell array 31, a bank address control circuit 35 connected to the fourth bus BABUS, for generating a real address according to the contents of the bank specifying register BP (BP0, BP1), and a selection circuit 37 for selecting the real address generated by the bank address control circuit 35, or the address provided through the second bus ABUS.

A microcontroller includes an electrically erasable and programmable nonvolatile memory and a memory controller for controlling the nonvolatile memory. Upon writing a control program for the microcontroller and data into the nonvolatile memory pursuant to an externally provided NVM command or an internally issued program command, a CPU of the microcontroller does not intervene in controlling the nonvolatile memory. Particularly, in a programming mode set by the external program command, CPU, buses, and communication interfaces of the microcontroller are deactivated. Further, the memory controller receives a NVM command, an address and data from outside of the microcontroller for controlling an operation of the nonvolatile memory based on the NVM command and the address without intervention of the CPU.

A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal.

A high-speed memory system is disclosed for use in supporting a directory-based cache coherency protocol. The memory system includes at least one data system for storing data, and a corresponding directory system for storing the corresponding cache coherency information. Each data storage operation involves a block transfer operation performed to multiple sequential addresses within the data system. Each data storage operation occurs in conjunction with an associated read-modify-write operation performed on cache coherency information stored within the corresponding directory system. Multiple ones of the data storage operations may be occurring within one or more of the data systems in parallel. Likewise, multiple ones of the read-modify-write operations may be performed to one or more of the directory systems in parallel. The transfer of address, control, and data signals for these concurrently performed operations occurs in an interleaved manner. The use of block transfer operations in combination with the interleaved transfer of signals to memory systems prevents the overhead associated with the read-modify-write operations from substantially impacting system performance. This is true even when data and directory systems are implemented using the same memory technology.

In one embodiment of the invention, a memory module is disclosed including a printed circuit board with an edge connector; an address controller coupled to the printed circuit board; and a plurality of memory slices. Each of the plurality of memory slices of the memory module includes one or more memory integrated circuits coupled to the printed circuit board, and a slave memory controller coupled to the printed circuit board and the one or more memory integrated circuits. The slave memory controller receives memory access requests for the memory module from the address controller. The slave memory controller selectively activates one or more of the one or more memory integrated circuits in the respective memory slice in response to the address received from the address controller to read data from or write data into selected memory locations in the memory integrated circuits.

A memory device includes a plurality of memory cells; a nonvolatile memory block suitable for simultaneously sensing one or more programmed weak addresses, and sequentially transmitting the sensed weak addresses; a weak address control block suitable for latching the weak addresses transmitted from the nonvolatile memory block, and outputting sequentially the latched weak addresses in a weak refresh operation; and a refresh control block suitable for controlling the memory cells corresponding to the counting address to be refreshed, in a normal refresh operation, and controlling the memory cells corresponding to the weak address to be refreshed, in the weak refresh operation.

For data protection in a wireless network system, a frame, including its Medium Address Control (MAC) header and payload, is encrypted with an initialization vector modified at each set state in a wireless network system, such that wirelessly transmitted data is prevented from being exposed to unauthorized users.

A memory includes a plurality of word lines each coupled to one or more memory cells, an address storage unit suitable for storing an address of a word line selected for access by a control unit among the plurality of word lines at a first time point; and the control unit suitable for sequentially refreshing the plurality of word lines in response to application of a refresh command, refreshing one or more adjacent word lines adjacent to a word line corresponding to the address stored in the address storage unit in response to every Nth application of the refresh command where N is a natural number and selecting one or more of the plurality of word lines for access, wherein the first time point is included in time section other than a refresh section in which the control unit refreshes one or more word lines in response to application of the refresh command.

The performance of a voice conference using a packet-based conference bridge can be improved with a number of modifications. In one modification, the conference bridge receives speech indication signals from the individual packet-based terminals within the voice conference, these speech indication signals then being used by the conference bridge to select the talkers within the voice conference. This removes the need for speech detection techniques within the conference bridge, hence decreasing the required processing power and the latency within the conference bridge. In another modification, the conference bridge sends addressing control signals to the individual packet-based terminals selected as talkers, these addressing control signals directing the terminals selected as talkers to directly transmit their voice data packets to the other terminals within the voice conference. This direct transmission of voice data packets can reduce transcoding and latency within the network. These two modifications could further be combined, resulting in a conference bridge that receives speech indication signals, selects the talkers for the voice conference and outputs addressing control signal to the talkers. In this case, the advantages of the two modifications are gained as well as additional capacity advantages resulting from no voice signals actually traversing the conference bridge.

Abstract of the Disclosure A page access circuit of a semiconductor memory device is normally operated even when a page address toggles at any timing in a page mode. The page access circuit comprises an address buffer, a column control unit, a page control unit, a pre-active unit and a precharge unit. The column control unit is controlled by the page address control signal. The page control unit controlled by a sense detecting signal is adapted and configured to generate the page address control signal. The pre-active unit controlled by the page address control signal is adapted and configured to generate a mode identification signal in response to the page address transition detecting signal. The precharge unit is adapted and configured to perform a selective precharge operation in response to the mode identification signal.

The present invention provides a RAM-incorporated driver that enables the writing of moving-image data to a RAM simultaneously with the writing of still-image data to a RAM, at a reduced energy consumption. The RAM incorporated X-driver IC receives still-image data from an MPU and moving-image data that is input by a separate system through a high-speed serial transfer line in accordance with the LVDS standard. An LVDS reception circuit suppresses the consumption of a steady current by which the differential input receiver operates, based on a data validation signal that becomes active when transfer data on the high-speed serial data transfer line from the MPU becomes valid. The still-image data and moving-image data that is received by separate systems is written to a RAM through first and second bus lines, respectively. Reading of still-image data and moving-image data, which is stored in a RAM, as display data is controlled by a display address control circuit.