105results about How to "Improve Phase Noise Performance" patented technology

The invention discloses a self-correcting phaselocked loop frequency synthesizer capable of realizing frequency band selection, composed of a phaselocked loop and a self-correction loop; wherein the phaselocked loop is formed by connecting a phase detection discriminator, a charge pump, a loop filter, a voltage-controlled oscillator and a frequency divider in sequence, the self-correcting loop is formed by connecting a phase detection discriminator, a trigger, a controller, a voltage-controlled oscillator and a frequency divider in sequence, and the phaselocked loop and the self-correcting loop share the same phase detection discriminator, the same voltage-controlled oscillator and the same frequency divider. The invention realizes center frequency correction by regulating one group of fixed capacitor of voltage-controlled oscillator, so that widen frequency tuning range can be obtained under lower gain of voltage-controlled oscillator, thus error caused by making process of integrated inductance and variable varactor can be compensated, phase noise of phaselocked loop frequency synthesizer is reduced, and implementation of single chip phaselocked loop frequency synthesizer by adopting CMOS technology can be realized.

The invention discloses a wireless sensor network application-oriented low-power consumption radio frequency receiving and sending device which comprises a duplexer, a radio frequency front end, a variable gain complex filter, an automatic frequency tuning circuit, a programmable gain amplifier, a phase-locked loop frequency synthesizer, a digital processor, a storage, a variable gain power amplifier, a mixer and a low pass filter, wherein the duplexer, the radio frequency front end, the variable gain complex filter, the automatic frequency tuning circuit and the programmable gain amplifier form a receiving link which is used for receiving and processing a radio frequency signal and converting the radio frequency signal into a low-medium frequency digital signal so that the signal can be conveniently processed by a subsequent analog-digital converter later; the duplexer, the variable gain power amplifier, the mixer and the low pass filter form an emitting link which is used for mixing a baseband analog modulation signal into a carrier frequency and sending a wireless signal; and the receiving link and the emitting link share the duplexer. The wireless sensor network application-oriented low-power consumption radio frequency receiving and sending device realizes singlechip integration by adopting a standard CMOS (Complementary Metal Oxide Semiconductor) process, is simple in structure and low in power consumption, and is applicable to a wireless sensor network.

A system for generating in-phase and quadrature phase signals is provided. The system includes a first and a second differential output, such as from a sinusoidal oscillator. A first injection-locked frequency divider, such as one that uses an LC oscillator in conjunction with cross-coupled transistors, receives the first differential output and generates a in-phase or in-phase output. A second injection-locked frequency divider receives the second differential output and generates a quadrature phase output.

A gyrator includes shunt or feedback nodal capacitors and shunt lossy inductors without shunt load resistors. The effective nodal capacitance is reduced by the introduction of the shunt lossy inductors. The inductors act to discriminate against injected power supply noise, resulting in improved oscillator phase noise. The inductors produce less dc voltage drop than the resistive load, so that larger linear oscillation is obtained with improved oscillator phase noise. The gyrator includes an automatic gain control circuit and a tuning control circuit which are separate from each other and fast and slow acting control loops which are augmented with each other.

A new all digital PLL (ADPLL) circuit and architecture and the corresponding method of implementation are provided. The ADPLL processes an integer and a fractional part of the phase signal separately, and achieves power reduction by disabling circuitry along the integer processing path of the circuit when the ADPLL loop is in a locked state. The integer processing path is automatically enabled when the loop is not in lock. Additional power savings is achieved by running the ADPLL on the lower-frequency master system clock, which also has the effect of reducing spur levels on the signals.

The invention discloses a millimeter-wave phase-locked loop, which comprises a voltage-controlled oscillator, an orthogonal output injection locked frequency divider, a charge pump and a loop filter, wherein the voltage-controlled oscillator is used for generating an oscillating signal of a set frequency by adopting a differential input tuning way; the orthogonal output injection locked frequency divider is used for performing frequency division processing on the oscillating signal to output multiple paths of orthogonal frequency division signals; the charge pump is used for converting a pulse signal into an analog voltage signal for realizing differential output; the loop filter is connected between the charge pump and the voltage-controlled oscillator, and is used for filtering an analog voltage signal output by the charge pump to input into the voltage-controlled oscillator. The millimeter-wave phase-locked loop is used for supplying a local oscillator signal of a set frequency to a 60GHz millimeter-wave communication system. According to the structure of the differential tuning voltage-controlled oscillator in the phase-locked loop, the noise of the oscillator is optimized, and the noise optimization of the entire phase-locked loop is facilitated greatly. A differential input control voltage is provided for a differential voltage-controlled oscillator through the charge pump, so that higher phase noise performance is achieved.

An oscillator having a plurality of operatively coupled ring oscillators arranged in hyper-matrix architecture. The operatively coupled ring oscillators are either identical or non-identical and are coupled through a common inverter or tail current transistors. Due to the arrangement of the ring oscillators in a hyper-matrix structure, the ring oscillators are synchronized and resist any variation in frequency or phase thereby maintaining a consistent phase noise performance

An LC-VCO includes a multivibrator which outputs a frequency signal, a fine tuning circuit which tunes the frequency signal by a first amount, a coarse tuning circuit which tunes the frequency signal by a second amount, and a control circuit which controls the fine and coarse tuning circuits. The coarse tuning circuit is formed from one or more capacitive arrays and the fine tuning circuit is formed from one or more varactors. The capacitive arrays are preferably controlled by a digital signal, where each bit selectively couples a respective capacitor to the multivibrator. An analog signal controls the value of the varactors. The capacitive arrays and varactors charge and discharge an inducator in the multivibrator to tune the frequency signal. The VCO may be incorporated within a phase-locked loop, where the capacitors may be assigned different weight and / or redundancy values to tune an output frequency signal. In one embodiment, coarse tuning and lead-lag detection is performed more accurately to allow the size of the varactors to become significantly reduced compared with other circuits which have been proposed.

The invention provides an all-digital fractional-N phase-locked loop structure comprising a time-digital converter TDC, a digital filter DLF, a digital-controlled oscillator DCO, a digital-controlled phase interpolator DPI, a sigmadelta modulator SDM, an integer frequency divider DIV and a feedforward correction module. Conversion from digital control signals to phase information is completed by using the digital-controlled phase interpolator DPI, and the nonlinearity brought by the DPI can be eliminated by using the feedforward correction means. According to the structure, the complexity of the circuit design can be reduced, and the problems of high power consumption, complex design and poor noise in the existing structure can also be solved so that the structure is suitable for the field of high-performance and low-power-consumption wireless communication.

The voltage-controlled oscillator (VCO) in a frequency synthesizer using a phase-locked loop (PLL) is calibrated digitally during power up. The VCO has a coarse frequency control and a fine frequency control. The coarse control is a digital phase-locked loop to quantize the broad frequency range into limited number of frequency steps with a clock frequency divided from the VCO frequency, and to hold the phase-locked dc control voltage for the fine control. By limiting the number of frequency steps and clocking at a divided frequency of the VCO, the coarse control is speeded up. The fine control is [connected to the charge pump output as in] a regular PLL. By searching for the optimal control setting, the center frequency of the VCO is trimmed close to the wanted frequency for the PLL to lock. This allows small VCO gain without losing the tolerance of process and temperature variations. As a result, the PLL phase noise performance is improved.

A voltage controlled oscillator including an RF output terminal and a DC control terminal, an active circuit, and a resonant circuit interconnected with the active circuit and including a plurality of series resonators each having an electrically variable capacitance and fixed inductor; the active circuit includes at least one transistor having an operating current density which is approximately 35% or less of the peak fT operating current density and / or the active circuit includes a multi-transistor bank disposed in at least two separate sections, each pair of sections spaced apart to provide improved thermal uniformity among the transistors without substantially increasing parasitic impedance among them for providing an improved lower phase noise output at said RF output terminal.

The invention relates to a voltage controlled oscillator, which comprises four transistors, an integrated on-chip inductor and two symmetric variable capacitors, wherein, two transistors realize negative resistance through cross coupling, thereby providing energy to oscillate an LC circuit comprising the inductor and the variable capacitors; by changing the capacitance of the variable capacitors, different output frequencies of the oscillator are obtained. The invention also comprises two resistors with the same value and two capacitors with the same value; a grid terminal of one of the rest transistors is connected with a terminal of a resistor and a terminal of a capacitor at the same time, which jointly form an active inductor; a grid terminal of the last transistor is connected with a terminal of a resistor and a terminal of a capacitor at the same time, thus jointly forming another active inductor; the two active inductors provide bias current for the voltage controlled oscillator. The invention enlarges the tuning range of the voltage controlled oscillator and reduces the phase noise.

The invention belongs to the technical field of radio frequency wireless receiver integrated circuits, and relates to a quadrature voltage controlled oscillator in a wireless receiver integrated circuit. In the quadrature voltage controlled oscillator, the phase noise performance of the quadrature voltage controlled oscillator circuit is improved and the output phase mismatch is reduced by improving a coupling mode of the conventional quadrature voltage controlled oscillator and introducing a phase shift network at the source end of a coupling tube. By using a linearly changed an accumulation-type metal-oxide semiconductor (MOS) variable capacitor array, the linearity of a tuning curve of a quadrature voltage controlled oscillator (QVCO) is greatly improved so that the tuning range of a control voltage is increased. Because a bias current of the QVCO is variable, a relatively constant output oscillating voltage amplitude can be maintained; therefore, a low phase noise can be obtained by the QVCO in a broad output frequency range.

An integrated voltage controlled oscillator is provided. The integrated voltage controlled oscillator includes a first slab inductor having two ends and a second slab inductor having two ends. A first oscillator core is connected to a first end of the first slab inductor and a second end of the second slab inductor, and a second oscillator core is connected to a second end of the first slab inductor and a first end of the second slab inductor. In this manner, the low-loss slab inductors provide the oscillator tank inductance.

The invention provides a VCO tuning curve compensation method. In the method, a negative resistance amplifier and an inductor are connected with both ends of a variable capacitor to form a parallel-connection structure, wherein the variable capacitor structure is a five-end AMOS capacitance network, and one end is a tuning curve compensation control end of the AMOS capacitance network, which changes the equivalent capacitance of the AMOS capacitance network by adjusting the DC voltage of a control end to obtain an approximate linearized change curve with respect to VCO output frequency and VCO control voltage, thereby realizing the VCO tuning curve compensation, improving the VCO stability and enabling a VCO circuit module to work in the area having a higher Q value. The invention also provides a VCO circuit module of a differential circuit structure formed by the method. The AMOS capacitance network comprises four AMOS varactors and one RC low-pass filter, wherein the four AMOS varactors are connected in series two by two and are symmetrically arranged, and the specific arrangement mode includes grid electrode series connection and substrate series connection. The VCO module performs voltage control on the AMOS varactors to change the oscillator frequency, and realizes the tuning curve compensation to enable the frequency tuning curve to be approximately linearized by changing the DC voltage of the compensation control end of the tuning curve, thereby realizing a larger frequency tuning range.

An oscillator, comprising: a pair of transistors to which source terminals are interconnected and to which drain and gate terminals are coupled by a positive feedback loop comprising an oscillator tank, wherein the source terminals of the transistors are connected to a current source configured to control physical parameters of the oscillator.

A quadrature LC tank based digitally controlled ring oscillator (DCO). The oscillator structure incorporates a plurality of stages, each stage including a buffer and a series LC tank. Four stages are coupled together to create a 360 degree phase shift around a loop. The oscillation frequency of the oscillator is the same as the resonant frequency of each LC tank, therefore it avoids quality factor degradation of LC tanks found in the prior art. In one example embodiment, class-D amplifiers are used to drive each of the LC tanks Capacitor banks before at the input and output of the buffers provide coarse and fine tuning of the frequency of oscillation. The high efficiency exhibited by these amplifiers results in very good phase noise performance of this oscillator. The oscillator utilizes a startup circuit to launch oscillation upon power on.

The invention belongs to the technical field of a radio frequency wireless transceiver and particularly relates to a frequency synthesizer suitable for a software radio system. The frequency synthesizer provided by the invention comprises module circuits such as a phase frequency discriminator (PFD), a charge pump, a loop filter, a voltage-controlled oscillator, a programmable frequency divider, a sigma-delta modulator, an automatic frequency calibration circuit, an orthogonal output frequency-halving divider and the like, can cover each frequency range of protocols such as WCDMA (wideband code division multiple access), GSM (global system for mobile communication), TD-SCDMA (time division-synchronization code division multiple access) and the like and is suitable for the software radio system. Compared with the traditional frequency synthesizer, the frequency synthesizer provided by the invention has the improvements in the aspects of voltage-controlled oscillator structure, loop design, automatic frequency calibration algorithm and the like to realize better phase noise and frequency spectrum stray performance and has short locking time.

The voltage-oscillator (VCO) in a frequency synthesizer using a phase-locked loop (PLL) is calibrated during power up or channel switching. The VCO has a coarse frequency control and a fine frequency control. The coarse control consists of digital bits that are used for calibration. The coarse control is connected to the charge pump output as in a regular PLL. By searching for the optimal control setting, the center frequency of the VCO is trimmed close to the desired frequency for the PLL to lock. This allows small VCO gain without losing the tolerance of process and temperature variations. As a result, the PLL phase noise performance is improved.

The invention relates to a low-phase noise frequency source. The low-phase noise frequency source includes a low-phase noise reference source which sends low-phase noise 400MHz reference signals and low-phase noise 1000MHz reference signals to a DDS and control module and sends low-phase noise 400MHz excitation signals to a harmonic generation module, the DDS and control module which sends low-phase noise baseband signals to an output module and sends control signals to the output module and the harmonic generation module, the harmonic generation module which sends low-phase noise local vibration signals to the output module, and the output module which performs frequency mixing, filtering and frequency division on the baseband signals and the local vibration signals so as to obtain low-phase noise 5MHz-1000MHz signals which are adopted as output signals. The low-phase noise frequency source of the invention has the advantages of wide band, low stray degree, fine resolution and the like.

A tunable multiphase ring oscillator includes a plurality of stages connected in series in a ring structure, where each stage generating a stage output from a stage input. Each stage of the tunable multiphase ring oscillator includes a plurality of trans-conductance cells, each generating an output from at least one portion of the stage input. Each stage further includes at least one phase shifting module for imparting at least one phase shift to the at least one portion of the stage input, an oscillator unit for generating the stage output from a combination of the plurality of outputs, and means for varying at least one of the plurality outputs so as to adjust a phase of the stage output.

A zero or near zero IF frequency changer for use in a digital tuner comprises multipliers which receive the RF input signal from an input. The multipliers receive quadrature local oscillator signals from a first oscillator of an arrangement which comprises first and second phase-locked loops. The first phase-locked loop comprises a programmable divider, a comparator and a control loop so that the first oscillator is phase-locked to a second oscillator. A second phase-locked loop comprises the second oscillator and a synthesizer containing a reference oscillator to which the second oscillator is phase-locked. The output frequency of the second oscillator is in a frequency band which is outside the RF input frequency band of the frequency changer.

A high power laser with chirped pulse amplification to produce extremely high power ultrashort pulses is disclosed. A pulse stretcher and methods of stretching a laser pulse are also disclosed. The pulse stretcher comprises: a first diffraction grating (G1) arranged to receive and disperse a seed laser pulse; transfer optics (CM) arranged to collect the dispersed pulse and direct it to a transmission diffraction grating (G2) which is either the first diffraction grating or a second diffraction grating; the transmission diffraction grating arranged to collimate the collected pulse to a reflector (BM), the reflector arranged such that the pulse is reflected back through the pulse stretcher via the transmission diffraction grating. The pulse stretcher provides better phase noise performance of the output pulse, and therefore a reduction in the noise floor to improve contrast pedestal.

In one aspect, a voltage controlled oscillator is provided that includes circuitry comprising tunable coupled resonator networks, which are coupled to a terminal of a pair of three-terminal devices through a tuning voltage network which supports wide-band tunability. In another aspect, a wide-band tunable resonator is provided that is amenable to integration in the integrated circuit form.

A quadrature VCO includes two cross-coupled differential pairs, two parallel LC tank circuits, two LO units and a plurality of source followers, supplying by a tail current source and a tail capacitor. The LC tank circuit constitutes of symmetrical spiral inductors and differential varactors, which constitutes of common anode diodes. The quadrature VCO circuitry is implemented on a chip with 2.4 GHz operating frequency. The quadrature VCO generates quadrature LO signals with high phase accuracy and good gain match under low power, good phase noise and small chip area, thus it can be applied to a variety of integrated transceivers.

This invention relates to the application method of frequency synthesis device in OFDM system, which is applied extensively in OFDM communication system, and it uses DDS combining with phase-locked loop to provide radio-frequency radical frequency for the frequency circuit in OFDM system. The frequency part directly in OFDM communication system adjusts carrier frequency deviation of the sender and collector. The advantage in this invention is that it has higher frequency differential rate, better phase noise character and wider frequency restricted portion and so on; it changes the output frequency rate of the frequency synthesis device to decrease the communication system carrier frequency deviation and lower the complexity of the synchronous algorithm of the base strip portion. The frequency synthesis device's trimming is obtained by changing DDS's frequency control character with microprocessor. This invention also designs elliptic low pass filter and low loop filter with fountain to provide better phase noise and frequency restricted portion character.

A voltage controlled oscillator is provided. The oscillator has an oscillator amplifier core formed of a complementary pair of FETs connected with their gates in common and connected to share a bias current. An inductance is connected between the common gates and the common drains of the FETs. The inductance may be an inductor element or an inductance of a physical structure of the circuit, such as a bond wire. The voltage controlled oscillator includes a variable capacitor stage connected at the input of the oscillator amplifier stage and a buffer amplifier stage connected at the output of the oscillator amplifier stage. The buffer amplifier of one embodiment includes a pair of complementary FETs having common gates connected to the common drains of the FETs of the oscillator amplifier stage. The buffer amplifier stage also include an inductor and a capacitor connected between common drains of the buffer amplifier FETs and the output.