493 results about "Buffer amplifier" patented technology

An EER amplifier for amplifying an RF signal includes: (II) a first RF amplifier for amplifying the phase portion of the signal; (III) an EER modulator for amplifying the envelope or baseband portion of the signal, including: A) a high frequency operational amplifier; B) a power amplifier; C) a feedback control loop including:

• • • • (1) a current-to-voltage conversion amplifier having an input coupled to a current monitoring output of the power amplifier and an output,
      • (2) an input buffer amplifier having an input coupled to receive the envelope signal and an output;
      • (3) a summing amplifier having: (a) an input coupled to the outputs of: (a) the current-to-voltage conversion amplifier and (b) the input buffer amplifier, and (b) an output coupled to the current control input of the power amplifier.

A pixel comprises a photo-sensitive element for generating charges in response to incident radiation and a sense node. A transfer gate is positioned between the photo-sensitive element and the sense node for controlling transfer of charges to the sense node. A reset switch is connected to the sense node for resetting the sense node to a predetermined voltage. A first buffer amplifier has an input connected to the sense node. A sample stage is connected to the output of the first buffer amplifier and is operable to sample a value of the sense node. A second buffer amplifier has an input connected to the sample stage. Control circuitry operates the reset switch and causes the sample stage to sample the sense node while the photo-sensitive element is being exposed to radiation. An array of pixels is synchronously exposed to radiation. Sampled values for a first exposure period can be read while the photo-sensitive element is exposed for a second exposure period.

A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory module, is disclosed. The architecture has adjustable delay circuits in each signal line and a delay detector circuit which receives a clock signal from the buffer amplifier architecture at the input and at the output of the buffer amplifier architecture, and takes the phase difference between the two signals to produce a control signal for setting the variable delay time of the delay circuits. To ensure that the delay time set by the delay detector circuit is independent of variations in parameters of the DRAM memory chips, the feedback path routed to the input of the delay detector circuit has a reference line network of the same structure and having the same electrical properties as capacitance elements which terminate the line network routed to the DRAM memory chips and the reference line network, and which have the same capacitances as the signal inputs on the DRAM memory chips.

The image quality of a display device using a bottom gate TFT is improved. In particular, fluctuation in luminance is controlled and the frequency characteristic of a driver circuit is compensated by suppressing a change in amount of current flowing through an EL element which is caused by a change in surrounding temperature while the device is in use. A monitoring EL element is provided in addition to a pixel portion EL element. The monitoring EL element constitutes a temperature compensation circuit together with a buffer amplifier and the like. A current is supplied to the pixel portion EL element through the temperature compensation circuit. This makes it possible to keep the amount of current flowing through the pixel portion EL element constant against a change in temperature, and to control the fluctuation in luminance. An input signal is subjected to time base expansion to perform sampling with accuracy.

A reliable, safe, accurate, low noise, inexpensive, portable amplifier circuit is adapted to accurately amplify both AC and DC neural response signals. A patient or subject is electrically connected to a multi-channel system for electrically measuring the patient's AC and DC neural response signals at a plurality of locations using electrodes connected through a multi-electrode cable. The neural response signals are input to a digital DC amplifier to filter, amplify and digitize the neural response signals. Digitized neural response signals are converted to optical signals and transmitted via a fiber optic cable to an interface that is preferably connected to a patient stimulus generator (e.g., a Ganzfeld stimulator or pattern stimulator for multi-focal ERG). The system also includes a stand-alone computer such as an IBM® compatible Personal Computer (PC) for two-way communication with the interface via a standard data interface cable (e.g., a USB cable). In the preferred embodiment, a digital DC amplifier is worn by the patient and receives each neural response signal at a two-conductor balanced input; a surge suppression circuit limits excessive voltage transients at the input. The neural response signal is next input to a balanced buffer amplifier stage for impedance matching and the buffered neural response signal is then input to a balanced, adjustable pre-amplifier stage having an adjustable gain which can be varied (e.g., from ×1 to ×64). The buffered, amplified neural response signal is then digitized for storage in a memory and transmission to a fiber-optic digital transmission circuit. An adjustable impedance element generates a DC offset compensation signal used to control a D.C. offset compensation amplifier to generate an offset control signal for input to gain-adjustable pre-amplifier stage, to maximize sensitivity and usable dynamic range.

A DC/DC converter 100 has a DAC 40 that receives a code associated with desired processor operating voltage and sets the reference voltage on its output 41. The reference voltage (V_DAC) is boosted by the buffer amplifier 42 to center the droop along the median load. A sensed current signal I_CS 22 is proportional to the load current I_o 24 and can be either inductor current, or switch current, or diode (or synchronous switch) current. In all cases it is scaled down by the factor of gain G_c. A droop control feedback circuit includes an error amplifier 50. It has two inputs. In one embodiment the gain of the converter is by a signal inversely proportional to the processor clock frequency F_{CPU max} and transformed to the current I_DROOP 32 that creates the voltage drop across the resistor R1. The other input is coupled to the buffer amplifier output. As a result, the output voltage of the converter 50 is inversely proportionally to the load current and is invariant to the processor clock frequency changes associated with the processor mode switchover. Other embodiments modify the gain of the error amplifier, or offset the gain and hold the amount of droop constant.

An interface apparatus for fan monitoring and control includes a current source amplifier that generates a programmable current in response to its input voltages. Associated with an output capacitor, which is able to reduce noise, the programmable current drives the fan at a desired speed. The rotating fan induces a ripple signal in the output capacitor, which is fed to a band-pass amplifier to produce a tachometer pulse. Through a buffer amplifier, an input control signal combined with a thermal sensor signal has direct control over the current source amplifier. Alternatively, a PWM circuit having a comparator, a ramp oscillator and the output of the buffer amplifier drives the current source amplifier in switching mode. Since the ramp oscillator can be synchronized by the input, both analog and pulse signals can function as the input control signals.

A LED drive circuit equipped with oscillator 18, up/down counter 20, and DAC 22 in order to drive multiple LEDs 10(1)-10(m) in a block. Up/down counter 20 carries out count-up/down operations in sync with clock CLK sent from oscillator 18 during the ramping up/down of pulse-lighting of the LEDs. DAC 22 converts counter count value DN into analog voltage signal V_DAC and supplies it to the gate terminal of NMOS transistor 14 via low-pass filter 28 and buffer amplifier 24.

A radio frequency transceiver of single chip includes a radio frequency receiving part, a radio frequency sending part, a local oscillation part, a reference voltage source and a current bias part. A low noise amplifier, a mixer and a intermediate frequency amplifier possessed by the radio frequency receiving part, an automatic gain regulator adjusting the gain of the radio frequency receiving part according to the intension of the received signal, a power adjuster and a buffer amplifier of a delivered power possessed by the radio frequency sending part, a voltage controlled oscillator, a frequency synthesizer and a crystal oscillator possessed by the local oscillation part, the reference voltage source and the current bias part are integrated to the single chip. The single chip has an input end and an output end of the received signal, which are connected with the receiving part, a filtering end connected with a filter at the outside, an input end and an output end of a signal to be emitted, which are connected with an emission part and a clock signal output end, a signal control end and an oscillation signal input end which are connected with the local oscillation part. In this way, the integration of the radio frequency transceiver is improved greatly.

The invention provides a clock adjustment circuit and an adjustment method for a clock circuit. The clock adjustment circuit comprises a clock buffer amplifier, a phase discriminator and a duty cycle adjustment circuit, wherein the clock buffer amplifier is used for receiving an external differential clock signal, shaping the differential clock signal into a single-end square wave clock signal and outputting the single-end square wave clock signal; the phase discriminator is used for receiving the single-end square wave clock signal from the clock buffer amplifier and a feedback signal from the duty cycle adjustment circuit, comparing the phase of the single-end square wave clock signal with the phase of the feedback signal to acquire a phase difference, and outputting the phase difference; and the duty cycle adjustment circuit is used for adjusting the duty cycle of the feedback signal by using the phase difference to acquire an adjusted feedback signal. The differential signal is shaped into the single-end square wave clock signal, the single-end square wave clock signal is compared with the feedback signal to acquire the phase difference, and the duty cycle is adjusted according to the phase difference, so that the complexity of duty cycle adjustment and hardware implementation can be effectively reduced, phase errors and the ripple waves of control voltage can be reduced, and adjustment accuracy is improved.

Methods, circuits, and apparatuses are disclosed that provide a buffer amplifier with lower output noise by narrow banding the amplifier. To reinvigorate the speed of the narrow-banded amplifier, a boost-on signal is initiated. The boost-on signal dynamically and rapidly injects a substantial current into the amplifier's bias current network to speed up its slew rate, when the amplifier's inputs get unbalanced when being subjected to a large transient differential input signal. Subsequently, after the amplifier regulate itself and as the amplifier's inputs approach substantial balance, a boost-off signal dynamically injects a slow and decaying current (that converges to the level of static steady-state bias current) into amplifier's bias circuitry, instead of turning off the boost current rapidly, which improves the amplifier's settling time.

An integrated circuit for controlling a DC motor is disclosed. The integrated circuit includes at least one digital position and speed circuit (DPS) for providing measurements of speed, position, and direction of the motor, the DPS being in signal communication with the motor for receiving a pair of signals having a quadrature relationship; and at least one programmable gain amplifier (PGA) electrically coupled to the motor, the PGA being configured to receive a feedback signal indicative of current flowing through the motor and to apply a second signal to the motor for adjusting the speed of the motor; and at least two analog-to-digital converters (A/D), one A/D being used to quantize the output of the PGA for an off-chip processor; and another A/D to provide motor reference position from an analog sensor, such as a potentiometer; and at least two digital-to-analog converters (D/A), one D/A used to set the motor voltage; and another D/A used to set the motor current limit. The integrated circuit can be incorporated into a larger motor control loop which further includes a summing amplifier for providing the feedback signal to the motor that is indicative of current flowing through the motor; a buffer amplifier electrically for sensing the output current of the motor, and a processor for providing control signals to the system monolithic module and for receiving the measurements of speed, position, and direction of the motor.

A semiconductor device with reduced power consumption and a display device including the semiconductor are provided. The semiconductor device generates a bias voltage that is to be supplied to a buffer amplifier. When the display device displays a still image, a data signal for updating the image need not be supplied from the buffer amplifier to a pixel array in the next frame; therefore, the circuit is configured so that the buffer amplifier is brought into a standby state (temporarily stopped). Specifically, input of a reference current from a BGR circuit to the semiconductor is stopped and a bias voltage is applied from the semiconductor device to the buffer amplifier to temporarily stop the operation of the buffer amplifier.

A miniaturized, low power RF transmitter with a dual mode active on-chip antenna/inductor is disclosed in which antenna also serves as the oscillator inductor. Also disclosed is a miniaturized low power RF receiver with an on-chip antenna; and a RF transmitter system wherein an on-chip antenna is wirelessly coupled to an off chip patch antenna are disclosed. Advantageously, the TX chip is housed in a low loss, e.g. Low Temperature Co-fired Ceramic (LTCC) package with a patch antenna to provide a System-on-Package implementation comprising electromagnetic coupling between a RF TX chip comprising an integrated on-chip antenna and a package antenna. The on-chip antenna feeds the LTCC patch antenna through aperture coupling, thus negating the need for RF buffer amplifiers, matching elements, baluns, bond wires and package transmission lines, and significantly increases the gain and range of the module with respect to the on-chip antenna alone, without deterioration of the circuit performance and power consumption. Exemplary embodiments are disclosed which may be fabricated using standard CMOS technology, for operation in the 5 GHz U-NII band for applications such as miniaturized, low cost, low power wireless devices and sensor systems.

Circuits and methods to achieve a low-noise and low offset continuous sigma-delta modulator used e.g. for battery management are disclosed. Continuous integration of input is enabled by special switching principle of three parallel integrators. Precharging of integrator output in so called pre-run mode minimizes integrator leakage and non-ideal effects by connecting a Gm in pre-run mode either to input voltage or to a reference voltage depending this Gm is being used in a following clock period. Parasitic effects due to switching at first integration capacitor are minimized by using buffer amplifiers tracking the voltage on integration capacitors.