187 results about "Low offset" patented technology

A control circuit for controlling a hysteretic regulator to operate at substantially fixed frequency has a voltage offset circuit which receives a first feedback signal and generates a pair of upper and lower offset voltages; a control reference stage which receives a reference voltage and the upper and lower offset voltages and outputs upper and lower control reference voltages; and a window comparator which receives the upper and lower control reference voltages and an output voltage feedback signal and outputs a pair of upper and lower control voltages for controlling switching of the hysteretic regulator at a fixed frequency. The first feedback signal may be representative of a switching frequency, a temperature or an output voltage of the hysteretic regulator, for example. The voltage offset circuit may further receive a second and / or an additional feedback signal. The first, second and / or additional feedback signals further may be weighted. According to particularly useful embodiments of the invention, the control method for a hysteretic regulator may use both output voltage and switching frequency as primary feedback signals, thereby allowing the window limits (control voltages) to be positioned completely independently and in any possible configuration about the nominal voltage. In other words, the two window limits can be positioned symmetrically or asymmetrically about the nominal voltage, and at the same time the lower window limit can be positioned either below, above, or equal to the upper window limit.

A screening method and circuit for implementing a Physically Unclonable Function (PUF), and a design structure on which the subject circuit resides are provided. A plurality of field effect transistors (FETs) is coupled to a low-offset dynamic comparator and is respectively selected to provide a plurality of FET pairs. For each FET pair, a voltage offset to obtain a comparator output transition is identified and recorded. The recorded voltage offset for each FET pair is compared with a margin threshold value. Each FET pair having an identified voltage offset less than the margin threshold value is discarded or disabled for PUF response generation use.