269 results about "Common emitter" patented technology

A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.

A semiconductor device having sufficiently high heat dissipation performance while inhibiting an increase in the area of a chip is provided. In semiconductor device 1, a plurality of HBTs 20 and a plurality of diodes 30 are one-dimensionally and alternately arranged on semiconductor substrate 10. Anode electrode 36 of diode 30 is connected to emitter electrode 27 of HBT 20 via common emitter wiring 42. Diode 30 works as heat dissipating elements dissipating to semiconductor substrate 10 the heat transmitted through common emitter wiring 42 from emitter electrode 27, and also works as a protection diode connected in parallel between an emitter and a collector of HBT 20.

A proximity detector for detecting the presence of a coin or token in a coin chute, comprising a pair of axially aligned coils disposed on opposed sides of the chute; a common-emitter amplifier having a base and a collector providing a detector output, one of the coils being connected to the collector and the other of the coils being connected to the base.

The invention provides a CMOS energy gap reference circuit which can reduce disturbance. The inventive circuit comprises an input differential couple composed of PMOS tubes, a current mirror composed of NMOS tubes, a frequency compensation network composed of a capacitor C1 and a resistance R4, a filter network composed of a capacitor C2 and a resistance R5, a start circuit composed of a PMOS tube and a capacitor C3, a current source I1 for providing current to the differential couple, an addition circuit composed of resistance and transistor, and an input conversion circuit for switching and controlling the input. The input conversion circuit comprises a NMOS tube connected with the addition circuit and the differential input couple and a NMOS tube connected with the differential input grade and the common-emitter amplification grade. Since the input conversion circuit can convert the differential input couple continuously, the invention can reduce the reference error caused by disturbance.

An LED illumination device 1 for vehicle use includes an LED lamp 10, a circuit 5 for supplying a current to the LED lamp from a power supply mounted on the vehicle, and a current control unit 7 for controlling the current supplied to the LED lamp 10 so as to be inversely proportional to the environmental temperature of the LED lamp 10. In this manner, in the current supply circuit, an LED chip 11 is coupled to the collector of a common-emitter type transistor 15. The current control unit includes a PTC thermistor 21 and the PTC thermistor 21 is coupled to the base of the transistor 15, whereby a current supplied to the base is made small when the temperature of the PTC thermistor 21 becomes high. The PTC thermistor 21 is placed in a circumstance where the temperature thereof becomes same as the environmental temperature of the LED chip 11 at the time where the LED chip 11 is in an OFF state.

A memory cell comprises asymmetric retention elements formed of bipolar junction transistors integrated with a CMOS transistor. The BJT transistors of the retention element may be vertically stacked. In one embodiment, the N region of two adjacent NPN BJT transistors may be connected to ground and may form a common emitter of the NPN BJT transistors while the P region of two adjacent PNP BJT transistors may be connected to high voltage and may form a common emitter of the PNP BJT transistors. For further compactness in one embodiment a base of one transistor doubles as a collector of another transistor. The retention element may have only a single bit line and a single write line, with no negative bit line. In some embodiments, a single inverter and only three transistors may form the retention element. Memory space may be cut approximately in half.

The invention discloses a radio frequency power amplifier integrated on a same chip. The radio frequency power amplifier comprises two stages of amplifying circuits. An automatic biasing cascode CMOS amplifier is adopted in the first-stage amplifying circuit, and a SiGe HBT connected through a common emitter is adopted in the second-stage amplifying circuit. According to the radio frequency power amplifier, the withstand voltage, the isolation and the bandwidth of the circuits can be improved, the voltage swing and working current of the circuits can be improved, the gain and the maximum output power of the circuits can be improved, the frequency performance of the power amplifier can be improved, full-chip integration can be achieved, and accordingly, the integration degree is improved, cost is reduced, and the application is simplified.

An ionization apparatus according to the present invention has a mechanism for causing metal ions emitted from an ion emitter to attach to an introduced target gas so as to generate ions of the sample gas and emits the ions of the sample gas to a mass spectrometer. The mass spectrometer has a zone in which one or both of an electric field and magnetic field are formed. As the electrode for causing the generation of cleaning plasma in the ionization zone generating the ions of the sample gas, the ion emitter is used. The ion emitter causes the generation of plasma in connection with a hollow vessel and removes deposits on components facing the ionization zone by the plasma. The plasma cleaning process is performed consecutively at a suitable timing after the ionization process. Due to the above configuration, deteriorated performance in ionization can be restored in a short time, a memory effect can be prevented, and accurate mass spectrometry becomes possible. The ionization apparatus of the present invention is suitable for a mass spectrometry apparatus.

A common mode linearized input stage comprises NPN and PNP differential pairs biased with respective tail currents at respective common emitter nodes, with each pair connected to receive a differential input signal. A tail current modulation circuit generates complementary output currents as a function of the voltage difference between the common emitter nodes, and first and second tail current sources generate the tail currents as a function of the complementary output currents. The tail current modulation circuit and the first and second tail current sources are arranged such that the magnitudes of the tail currents increase with an increasing differential input signal.

The invention discloses a push-pull radio-frequency power amplifier with improved linearity and efficiency, comprising an input matching network, an output matching network and a power amplification circuit, wherein the power amplification circuit comprises a first-stage amplification circuit and a second-stage amplification circuit, the first-stage amplification circuit is connected with the input matching network, the second-stage amplification circuit is connected between the first-stage amplification circuit and the output matching network, and the second-stage amplification circuit is an NPN-NPN push-pull amplification circuit composed of a second common collector amplifying tube and a second common-emitter amplifying tube. The output matching network is an output filter matching network which comprises a secondary harmonic series resonance network, a third harmonic series resonance network and a stopping condenser, wherein the secondary harmonic series resonance network is connected between the output end of the second-stage amplification circuit and the ground, the third harmonic series resonance network is connected between the output end of the secondary harmonic series resonance network and the stopping condenser, and the stopping condenser is connected between the third harmonic series resonance network and the power amplifier. The invention improves the additional efficiency of the radio-frequency power amplifier and improves the linearity of the radio-frequency power amplifier.

The invention provides a high-gain and low-noise differential trans-impedance amplifier. The high-gain and low-noise differential trans-impedance amplifier comprises a current mirror, an adjusting type common-emitter and common-base trans-impedance amplifier and an output common-source amplifier, wherein the adjusting type common-emitter and common-base tarns-impedance amplifier comprises a common-base amplifying unit and a negative feedback common-emitter amplifying unit; the negative feedback common-emitter amplifying unit is arranged between an emitter and a base of the common-base amplifying unit and serves as a negative feedback channel; input current is copied by the current mirror in an equal proportion manner; the current mirror provides bias voltage for the common-base amplifying unit and the negative feedback common-emitter amplifying unit; the output common-source amplifier is connected between an output end of the adjusting type common-emitter and common-base trans-impedance amplifier and an output end of the high-gain and low-noise differential trans-impedance amplifier; and trans-impedance gain is increased. By the high-gain and low-noise differential tarns-impedance amplifier, received weak signals are amplified in a high-gain and low-noise manner, bandwidth is large, and a dynamic range of inputted current signals are reasonably set; and the high-gain and low-noise differential tarns-impedance amplifier has the advantages of easiness in design and monolithic integration.

Systems and methods for providing an adaptive bias circuit that may include a differential amplifier, low-pass filter, and common source amplifier or common emitter amplifier. The adaptive bias circuit may generate an adaptive bias output signal depending on input signal power level. As the input power level goes up, the adaptive bias circuit may increase the bias voltage or bias current of the adaptive bias output signal. A power amplifier (e.g., a differential amplifier) may be biased according to the adaptive bias output signal in order to reduce current consumption at low power operation levels.

The invention provides a radio frequency low amplifier with high linearity. The amplifier comprises an input common emitter gate, an output common bar gate, a load output matching network and a biasing circuit, wherein the biasing circuit comprises a charge pump feedback loop and a high linearity biasing circuit of a feed biasing circuit. The input common-emitter grade and the output common bar gate refer to hetero junction bipolar transistor (HBT)-metal-oxide-semiconductor field effect transistor (MOSFET) tubular structure in order to improve linearity and obtain good low noise performance. The biasing end of an input tube of the input common emitter gate is connected with the high linearity biasing circuit, the feed biasing circuit is a combination structure of a resistance feed biasing circuit and a diode feed biasing circuit. When a strong signal is inputted, the input tube provides a base current to compensate the decrease of voltage of a base electrode and an emitting electrode of the input tube. When a small signal is input, the charge pump feedback loop makes no contribution, the feed biasing circuit is in a regular work so that a constant biasing voltage is obtained, and therefore the linearity of the low noise amplifier is improved remarkably. The amplifier has the advantages of guaranteeing the performance of the low noise performance, improving greatly the linearity and achieving monolithic integration.

The invention discloses a single-converted-to-double low noise amplifier with a highly balanced and stabilized differential output gain phase. The amplifier comprises a common source or common emitter input amplifying transistor pair which comprises a first transistor and a fourth transistor, a common gate or common base amplifying transistor pair which comprises a second transistor and a third transistor, a tail current source pipe and output load circuits with tight coupling differential inductors; a fourth inductor L4 and a fifth inductor L5 are tight coupling differential inductors; C1 and C2 are differential capacitors with the same capacitance values; L0 and L1 also are tight coupling differential inductors. For the amplifier disclosed by the invention, since output loads adopt the tight coupling differential inductors L4 and L5 and the differential capacitors C1 and C2 for resonance, the balance and the stability of the differential output gain phase are improved, and the high-impedance tail current source pipe M5 can well restrain a common mode signal. The amplifier disclosed by the invention has excellent robustness when the PVT (Pressure Volume Temperature) and a working frequency point are changed, and at the same time, the amplifier has an excellent anti-interference capacity for the medium base noise.

The invention provides an ultra-wide-band low-noise high-balance on-chip active Balun.The matching characteristic in an ultra wide band is achieved at the input end of a whole circuit by adopting a wide-band matching network.A first-stage amplifier adopts a common-emitter common-base low-noise amplifier to decrease the noise coefficients of the whole active Balun, and an on-chip inductor is adopted for an output of the first-stage amplifier to compensate high-frequency grain.A second-stage amplifier adopts a differential amplifier of a Darlington unit, a resistance feedback technology is adopted between a collector electrode and a base electrode of each Darlington tube to ensure the working stability of the Darlington tubes, and a series inductor is introduced for tail current of a Darlington unit differential pair to compensate a tail-current parasitic capacitor so as to improve the balance of output differential signals.The isolation and direct-current potential shifting between the first-stage amplifier and the second-stage amplifier are achieved through an emitter follower.The ultra-wide-band low-noise high-balance on-chip active Balun has the advantages of being small in noise coefficient, large in bandwidth and high in balance.

The invention discloses a current feedback operational amplifier circuit comprising a power supply, a bias current supply unit, a first common base-common emitter current mirror, a second common base-common emitter current mirror, a static bias circuit, an input buffer stage, a voltage conversion stage and a drive output unit, wherein the drive output unit comprises a bias voltage circuit and an output buffer stage; the bias current supply unit is respectively connected with the input buffer stage through the first common base-common emitter current mirror and the second common base-common emitter current mirror and used for supplying bias current; and the static bias circuit is respectively connected with the inverted input end of the input buffer stage and the voltage conversion stage and used for stabilizing a static working point of the inverted input end. The current feedback operational amplifier circuit has the advantages of lower offset voltage, stronger on-load capacity and higher conversion rate and is beneficial to improvement of the precision and the linearity of the entire operational amplifier.

The present invention discloses a matrix V2G quick charge and discharge method. The method adopts an AC / DC matrix converter topology structure, and six bidirectional switches of the structure adopt common-emitter IGBTs. The method comprises four steps of carrying out sector partition and calculating sector angles and effective current duty ratios, setting conducting time for the corresponding bidirectional switch in each sector, performing quick charge by means of voltage-current double closed-loop space vector control, and performing constant-current discharge by means of current loop negative feedback control. The matrix V2G quick charge and discharge method according to the present invention solves the problems of high frequency of electric energy converting, low converting efficiency and long time for charging and discharging of the existing V2G converter. The matrix V2G quick charge and discharge method realizes quick charge and discharge of the storage battery for the electric automobile by means of pulse charging / constant-current discharging the storage battery based on an AC / DC matrix converter, the power factor is 1, and the harmonic distortion of grid-side current is decreased to below 5% by using the double zero vector switch sequences, so that the switching loss is effectively reduced, and the conversion efficiency is increased.

An IGBT module is configured with a plurality of IGBT cells connected to each other. The IGBT chips are each configured a plurality of unit cells connected to each other. The unit cells each include one IGBT element. Gate voltage is applied to the gate of the IGBT element from a common gate terminal through a gate pad and a gate resistor. Emitter voltage is applied to the emitter of the IGBT element from a common emitter terminal through an emitter pad. Collector voltage is applied to the collector of the IGBT element from a common collector terminal. The gate pad, gate transistor and emitter pad are provided for each of the unit cells. Thus obtained is an IGBT module capable of suppressing gate voltage oscillation without significantly increasing switching loss.

A multiplier having a simple constitution, excellent performance with respect to high-frequency characteristics and distortion characteristics, and allows low-voltage operation. Transistor Q11, resistors R11 and R12 form a common-emitter circuit. One signal of differential signal v1 is amplified by the common-emitter circuit, and the amplified signal is input to an emitter follower composed of transistor Q12. The output current of the emitter follower is input through resistor R13 into the current mirror circuit composed of transistors Q13 and Q14. Output current I5 of said current mirror circuit is input to the transistor pair of transistor Q19 and npn transistor Q20. By selecting an appropriate gain for the common-emitter circuit, currents I5 and I6 generated in this way become independent of the base-emitter voltage, and performance is improved with respect to distortion characteristics.

A variable gain amplifier circuit is provided so that an electric current decreases when a voltage gain is lowered and that the amplifier circuit is substantially free of a deterioration in distortion characteristics. The bases of bipolar transistors Q1, Q3 and Q5 and the bases of bipolar transistors Q2, Q4 and Q6 are connected in common with each other, these bipolar transistors forming a plurality of common-emitter amplifier circuits, and switches SW2, SW1 and SW0 are connected to the respective sides of the bipolar transistors. The emitter sides are held at a ground potential gnd by switching the switches SW2, SW1 and SW0 so that the voltage gain is controlled by selecting the common-emitter amplifier circuits different in voltage gain. A collector current I0 and an emitter degeneration resistance Re between the common-emitter amplifier circuits are so arranged as to have different values. The ratio of the collector current I0 is set inversely proportional to the ratio of the emitter degeneration resistance Re, whereby the collector current I0 decreases when the voltage gain is lowered and a deterioration in distortion characteristics is substantially obviated.

A communications system includes an optical receiver for receiving optical signals and for converting the optical signals into electrical signals, a transimpedance amplifier (“TIA”) for filtering the electrical signals, a limiting amplifier coupled with the TIA, an automatic threshold control (“ATC”) coupled with the TIA for providing a reference voltage for the limiting amplifier. The ATC further includes a common emitter circuit and an emitter follower circuit, wherein logic high signals and logical low signals in the electrical signals are determined based on the reference voltage output from the ATC.

A high frequency amplifier in which a common emitter bipolar transistor is used, and in that a constant current source and a constant voltage source are switched to apply a DC bias to a base terminal of the bipolar transistor in accordance with a power level of a high frequency signal input to the bipolar transistor or a power level of a high frequency signal output therefrom, and a frequency mixer in that a DC bias is applied to a base of at least one of a bipolar transistor for the input of a high frequency signal and a bipolar transistor for the input of a local oscillation wave by using a configuration for applying the DC bias to a base of an amplifying bipolar transistor employed in the high frequency amplifier.

The present invention provides a ramp generator capable of appropriately setting a rise starting point of an output voltage of a ramp waveform and an output voltage at the time of stable output. A current adjustment unit including a differential pair of transistors and an amplifier constitute a feedback circuit. By controlling the charging / discharging of an integration capacitor by ON / OFF of a discharge current source connected to a common emitter terminal of the current adjustment unit, an output of the ramp waveform outputted from an output terminal disposed at the connection end of the integration capacitor is controlled.

The invention belongs to the field of electronic technologies, and particularly provides a longitudinal-BJT-triggered SCR device used for ESD protection. The longitudinal-BJT-triggered SCR device (VBTSCR) introduces an extra triggering path on the basis of a traditional LSCR device. An ESD injection layer is introduced into a first conduction type well region, so as to form a longitudinal-structure base region floating NPN transistor. The ESD injection layer is a P-type doped region with a medium doping concentration, and the doping concentration thereof is between a drain / source heavily-dopedactive region concentration and a well region doping concentration. According to the SCR device, a common-emitter collector junction avalanche breakdown voltage BV<CEO> of the longitudinal-structurebase region floating NPN transistor is very low, when the base region floating NPN transistor serves as a triggering device of the SCR, significant reduction of the triggering voltage of the SCR device can be realized, thereby realizing the effect of providing effective ESD protection for circuits in an advanced nanometer technology.

An improved collector electrode for an electrostatic precipitation air filter including a voltage source, an ion emitter, insulated drive electrodes, and attraction electrodes. The insulated drive electrodes include a multi-part structure having an electrically conductive material located between non-electrically conductive portions. The insulated drive electrodes allow an increased voltage potential between the attraction electrodes and the drive electrodes.

Power amplifier having staggered cascode layout for enhanced thermal ruggedness. In some embodiments, a radio-frequency (RF) amplifier such as a power amplifier (PA) can be configured to receive and amplify an RF signal. The PA can include an array of cascoded devices connected electrically parallel between an input node and an output node. Each cascoded device can include a common emitter transistor and a common base transistor arranged in a cascode configuration. The array can be configured such that the common base transistors are positioned in a staggered orientation relative to each other.

The invention relates to the technical field of short-wave wireless communication and provides a short-wave high-linearity balance structure power amplifier. The short-wave high-linearity balance structure power amplifier comprises an input Balun, two same amplification circuit modules, an adjustable DC bias circuit module and an output Balun, wherein radio frequency input signals are coupled to two balance signals having a phase difference of 180 degrees through the input Balun, the two balance signals are respectively input to the two amplification circuit modules, output signals of the two amplification circuit modules are coupled to single-signal output through the output Balun, and the adjustable DC bias circuit module is used for providing DC bias for the two amplification circuit modules; each amplification circuit modules comprises an amplification circuit and a negative feedback circuit, each amplification circuit is composed of two transistors through cascading by use of a common-emitter and common-base mode, each negative feedback circuit is composed of a directional coupler, and the negative feedback circuits are connected with the input ends and the output ends of the amplification circuits. The power amplifier employs a balance structure, is simple in structure and also has the advantages of high linearity and high output power.

Methods and systems for split voltage domain receiver circuits are disclosed and may include amplifying complementary received signals in a plurality of partial voltage domains. The signals may be combined into a single differential signal in a single voltage domain. Each of the partial voltage domains may be offset by a DC voltage from the other partial voltage domains. The sum of the partial domains may be equal to a supply voltage of the integrated circuit. The complementary signals may be received from a photodiode. The amplified received signals may be amplified via stacked common source amplifiers, common emitter amplifiers, or stacked inverters. The amplified received signals may be DC coupled prior to combining. The complementary received signals may be amplified and combined via cascode amplifiers. The voltage domains may be stacked, and may be controlled via feedback loops. The photodetector may be integrated in the integrated circuit.

The invention discloses a radio frequency power amplifier, which is integrated on the same chip. The radio frequency power amplifier comprises an input matching network, a first stage amplifying circuit, an inter-stage matching network, a second stage amplifying circuit, an output matching network, a first biasing circuit and a second biasing circuit; and the two stage amplifying circuits both adopt SiGe HBTs (Heterojunction Bipolar Transistor) in common emitter connection. The radio frequency power amplifier disclosed by the invention can realize full-chip integration; and thus, the integration level is improved, the cost is reduced, the application is simplified, the voltage swing and the working current of the circuit can be improved, the gain and the maximum output power of the circuit can be improved, and the frequency performance of a component can be improved; and the SiGe HBT can adopt a high-voltage tube and has a relatively high withstand voltage, so the voltage endurance capability of the circuit can be improved.

The invention discloses a SiGe hetero junction transistor with polycrystal collecting region inverted structure, belonging to the semiconductor device structure and fabrication technology field. After avoiding a buried layer and an N- epitaxy Si layer structure in general SiGe HBT transistor, an underlay N+ layer is directly taken as an emitting area, and then a SiGe epitaxy base region, a polycrystal Si collecting area and an electronic device structure consisting of an emitter, a base electrode and a collector are in turn made. The collecting region is positioned on the upper layer of the structure, which contributes to adopting ion injecting technique to adjust the position of B-C junction, thereby well guaranteeing the performance of device. An outside base region and the down-lead of base electrode adopt a dielectric layer to separate from the lower emitting area, which reduces capacitance and guarantees the working speed of device. The transistor with the inverted structure is suitable for forming SiGe microwave monolithic integrated circuit in a form of common emitter.