1707 results about "Conduction type" patented technology

A semiconductor light-emitting element is provided which has a structure that does not complicate a fabrication process, can be formed in high precision and does not invite any degradation of crystallinity. A light-emitting element is formed, which includes a selective crystal growth layer formed by selectively growing a compound semiconductor of a Wurtzite type, a clad layer of a first conduction type, an active layer and a clad layer of a second conduction type, which are formed on the selective crystal growth layer wherein the active layer is formed so that the active layer extends in parallel to different crystal planes, the active layer is larger in size than a diffusion length of a constituent atom of a mixed crystal, or the active layer has a difference in at least one of a composition and a thickness thereof, thereby forming the active layer having a number of light-emitting wavelength regions whose emission wavelengths differ from one another. The element is so arranged that an electric current or currents are chargeable into the number of light-emitting wavelength regions. Because of the structure based on the selective growth, the band gap energy varies within the same active layer, thereby forming an element or device in high precision without complicating a fabrication process.

A silicon-on-insulator chip includes an insulator layer, typically formed over a substrate. A first silicon island with a surface of a first crystal orientation overlies the insulator layer and a second silicon island with a surface of a second crystal orientation also overlies the insulator layer. In one embodiment, the silicon-on-insulator chip also includes a first transistor of a first conduction type formed on the first silicon island, and a second transistor of a second conduction type formed on the second silicon island. For example, the first crystal orientation can be (110) while the first transistor is a p-channel transistor, and the second crystal orientation can be (100) while the second transistor is an n-channel transistor.

A semiconductor storage device comprises a semiconductor substrate; an insulating layer formed on the semiconductor substrate; a first semiconductor layer formed on the insulating layer and insulated from the semiconductor substrate; memory cells each having a source region of a first conduction type and a drain region of the first conduction type both formed in the first semiconductor layer, and having a body of a second conduction type formed in the first semiconductor layer between the source region and the drain region, said memory cells being capable of storing data by accumulating or releasing electric charge in or from their respective body regions; memory cell lines each including a plurality of said memory cells aligned in the channel lengthwise direction; and a memory cell array including a plurality of said memory cell lines aligned in a channel widthwise direction of the memory cells, wherein said memory cells on a common memory cell line are aligned to uniformly orient the directions from their source regions to the drain regions whereas directions of said memory cells from their source regions to the drain regions on said memory cell line are opposite from those of memory cells on neighboring said memory cell lines.

A heat conduction-type sensor corrects (calibrate) effects of a temperature of a measurement target fluid and a type of the fluid on a measurement value in measurement of a flow velocity, a mass flow, or an atmospheric pressure. Also provided is a thermal flow sensor and a thermal barometric sensor with this correcting function, high sensitivity, simple configuration, and low cost. At least two thin films that are thermally separated from a substrate through the same cavity are provided, one thin film comprises a heater and a temperature sensor, and the other thin film comprises at least one temperature sensor, the temperature sensors being thin-film thermocouples. The thin film is arranged in proximity so that it is heated only through the measurement target fluid by heating of the heater. A calibration circuit calculates and compares quantities concerning heat transfer coefficients of a standard fluid and the unknown measurement target fluid.

A strained crystalline layer having a tensilely strained SiGe portion and a compressively strained SiGe portion is disclosed. The strained crystalline layer is epitaxially bonded, or grown, on top of a SiGe relaxed buffer layer, in a way that the tensilely strained SiGe has a Ge concentration below that of the SiGe relaxed buffer, and the compressively strained SiGe has a Ge concentration above that of the SiGe relaxed buffer. The strained crystalline layer and the relaxed buffer can reside on top a semi-insulator substrate or on top of an insulating divider layer. In some embodiments the tensile SiGe layer is pure Si, and the compressive SiGe layer is pure Ge. The tensilely strained SiGe layer is suited for hosting electron conduction type devices and the compressively strained SiGe is suited for hosting hole conduction type devices. The strained crystalline layer is capable to seed an epitaxial insulator, or a compound semiconductor layer.

A method of manufacturing a semiconductor article comprises steps of forming a diffusion region at least on the surface of one of the sides of a silicon substrate by diffusing an element capable of controlling the conduction type, forming a porous silicon layer in a region including the diffusion region, preparing a first substrate by forming a nonporous semiconductor layer on the porous silicon layer, bonding the first substrate and a second substrate together to produce a multilayer structure with the nonporous semiconductor layer located inside, splitting the multilayer structure along the porous silicon layer but not along the diffusion region and removing the porous silicon layer remaining on the split second substrate.

A semiconductor device includes a cylindrical main pillar that is formed on a substrate and of which a central axis is perpendicular to the surface of the substrate, source and drain diffused layers that are formed in a concentric shape centered on the central axis at upper and lower portions of the main pillar and made from a first-conduction-type material, a body layer that is formed at an intermediate portion of the main pillar sandwiched between the source and drain diffused layers and made from the first-conduction-type material, and a front gate electrode that is formed on a lateral face of the main pillar while placing a gate insulating film therebetween. Moreover, a back gate electrode made from a second-conduction-type material is formed in a pillar shape penetrating from an upper portion to a lower portion on an inner side of the main pillar.

A solar cell element having improved power generation efficiency is provided. A solar cell element 100 has a substrate 110, a mask pattern 120, semiconductor nanorods 130, a first electrode 150 and a second electrode 160. The semiconductor nanorods 130 are disposed in triangular lattice form as viewed in plan on the substrate 110. The ratio p / d of the center-to-center distance p between each adjacent pair of the semiconductor nanorods 130 and the minimum diameter d of the semiconductor nanorods 130 is within the range from 1 to 7. Each semiconductor nanorod 130 has a central nanorod 131 formed of a semiconductor of a first conduction type, a first cover layer 132 formed of an intrinsic semiconductor and covering the central nanorod 131, and a second cover layer 138 formed of a semiconductor of a second conduction type and covering the first cover layer 132.

In order to improve reliability by preventing an edge breakdown in a semiconductor photodetector having a mesa structure such as a mesa APD, the semiconductor photodetector comprises a mesa structure formed on a first semiconductor layer of the first conduction type formed on a semiconductor substrate, the mesa structure including a light absorbing layer for absorbing light, an electric field buffer layer for dropping an electric field intensity, an avalanche multiplication layer for causing avalanche multiplication to occur, and a second semiconductor layer of the second conduction type, wherein the thickness of the avalanche multiplication layer at the portion in the vicinity of the side face of the mesa structure is made thinner than the thickness at the central portion of the mesa structure.

The present invention discloses a vertical junction structure with multi-PN channels, which provides a maximum interface between p-type and n-type materials in order to assist the charge separation, and offers continuous phases in both p- and n-type materials for charge transport in opposite directions.The present invention also provides methods for constructing the device structures. The main steps include 1) assembling a porous structure or a framework with semiconductor materials of one conduction type on a first electrode, 2) filling pores or coating the framework made from the materials in step 1 with semiconductors or precursors of conducting polymer of a opposite conduction type, 3) chemically and physically treating the system to form closed packed multi-PN channels.

A semiconductor device comprises on a surface of a first semiconductor layer of the first conduction type a second semiconductor layer of the first conduction type. A semiconductor base layer of the second conduction type is formed on the second semiconductor layer, and a semiconductor diffusion layer of the first conduction type is formed on a surface of the semiconductor base layer. A trench is formed from the surface of the semiconductor diffusion layer to a depth reaching the second semiconductor layer. A gate electrode is formed of a conductor film buried in the trench with a gate insulator interposed therebetween. The conductor film includes a first conductor film formed along the gate electrode to have a recess and a second conductor film formed to fill the recess.

A pixel circuit includes a pixel electrode, a pixel transistor of a first conduction type, and a flip-flop. The pixel transistor has a control node connected to a scanning line, a first node connected to a data line, and a second node. The flip-flop has an inverter and a feedback transistor of a second conduction type opposite to the first conduction type. The inverter has an input node connected to the second node of the pixel transistor, and an output node connected to the pixel electrode. The feedback transistor is controlled to be turned on or off in accordance with an output of the inverter for supplying a high-level power source voltage or a low-level power source voltage to a common connection point of the second node of the pixel transistor and the input node of the inverter, in the ON state.