344 results about "Ramp generator" patented technology

A system and method for delivering regulated power and current to an output load has a flyback transformer having a primary winding and a secondary winding. The secondary winding delivers stored energy to the output load. An oscillator circuit is provided for generating a periodical signal. A switching circuit is coupled to the flyback transformer and the oscillator circuit for energizing the primary winding to a reference current level each cycle of the oscillator circuit. The oscillator circuit has an integrator for deriving a time integral of a voltage at the primary winding. The oscillator circuit has a peak detector coupled to the integrator for holding a peak value of the time integral. The oscillator circuit further has a ramp generator for producing a ramp signal. A comparator is provided for comparing the peak value with the ramp signal and generating the periodical signal whenever the ramp signal exceeds the peak value.

A control system that can accommodate the wide variations in the output of a generator, such as a permanent magnet alternator, while providing an output with relatively uniform phase ripple. The control system includes a zero crossing detector and variable ramp generator for generating control signals to a switching rectifier to generate a regulated DC signal.

A system and method for delivering regulated power and current to an output load has a flyback transformer having a primary winding and a secondary winding. The secondary winding delivers stored energy to the output load. An oscillator circuit is provided for generating a periodical signal. A switching circuit is coupled to the flyback transformer and the oscillator circuit for energizing the primary winding to a reference current level each cycle of the oscillator circuit. The oscillator circuit has an integrator for deriving a time integral of a voltage at the primary winding. The oscillator circuit has a peak detector coupled to the integrator for holding a peak value of the time integral. The oscillator circuit further has a ramp generator for producing a ramp signal. A comparator is provided for comparing the peak value with the ramp signal and generating the periodical signal whenever the ramp signal exceeds the peak value.

A DC-DC converter including a Pulse Width Modulation (PWM) controller for converting an input voltage into an output voltage is provided. The PWM controller includes an error amplifier, a comparator, a PWM generator and a ramp generator. The error amplifier generates an error signal according to a difference between a reference voltage and the output voltage. The comparator compares the error signal with a ramp signal to generate a trigger signal. The PWM generator generates a PWM signal with a fixed turn-on time, wherein a frequency of the PWM signal is adjusted according to the trigger signal, the input and output voltages. The ramp generator generates the ramp signal according to the PWM signal, the input voltage and the output voltage.

A ramp generator includes a resistance ladder supplied with a constant current. Switches are closed in sequence by a shift register to provide a stepped ramp output. The constant current is controlled by referencing an on-chip bandgap voltage that is used as an input to a feedback circuit controlling current through a reference resistor ladder.

Synchronously stackable double-edge modulated pulse width modulation generators are disclosed. An example pulse width modulation generator includes a ramp generator to generate first and second ramp signals that interact to form a virtual ramp signal; and a comparator module coupled to the ramp generator configured to produce a pulse width modulated signal based on a comparison between the virtual ramp signal and an input signal.

A Class D amplifier comprises a ramp generator that generates a first reference signal and a second reference signal. A signal generator generates a first signal as the first reference signal exceeds an input signal to the Class D amplifier and generates the first signal as the second reference signal exceeds the input signal. The signal generator generates a second signal as the first reference signal falls below the input signal and generates the second signal as the second reference signal falls below the input signal.

System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate.

A current replication circuit that avoids the LEB period restriction of a DC-DC boost converter. The DC-DC boost converter regulates an output voltage by switching an input voltage through an inductor and a diode using a switch controller employing current feedback control and providing a PWM signal to control a switch coupled to the inductor. The current replication circuit includes a current sensor, a ramp generator, and a summing device. The current sensor samples current through the inductor while the switch is off and provides a sample voltage indicative of inductor current just before the switch is turned on. The ramp generator provides a ramp voltage replicating current increase of the inductor while the switch is on. The summing device adds the sample voltage to the ramp voltage to develop a replication voltage used for feedback current control by the switch controller.

A control device for a switching power supply includes an frequency-hopping oscillator for generating an oscillating signal and an indication signal, an SR flip flop for outputting a driving signal according to the oscillating signal and the indication signal, to control a primary winding of a transformer of the switching power supply, a comparator for comparing a current sense signal of the primary winding and a subtraction result, to output the comparison result to the SR flip flop, a ramp generator for generating ramp signals with time-varying slopes, and a subtraction unit for performing a subtraction operation on a feedback signal and the ramp signals, to generate the subtraction result for the comparator.

A system for controlling a weld-current in an arc welding apparatus for short arc welding comprising a current regulator included in a voltage feedback loop from a power supply to a welding electrode and a ramp generator arranged to provide current ramps during a short circuit phase at said welding electrode.

Peak current, valley current or average current mode controlled power converters in either digital or analog implementations obtain a stabilized feedback loop and allow high system bandwidth design by use of an external ramp generator using a slope computation equation or design parameters based on fixing the quality factor of a double pole at one-half of the switching frequency at a desired value The slope of the external ramp waveform is tuned automatically with knowledge of the slope change in the waveform of inductor current of a power converter derived by differentiating a waveform in the current feedback loop. This autotuning of the external ramp generator provides immunity of quality factor change under variations of duty cycle, component values of topological change of the power converter.

The present invention discloses a current balance circuit for a multiphase DC-DC converter. The current balance circuit comprises a current error calculation circuit, for generating a plurality of current balance signals indicating imbalance levels of a plurality of inductor currents of a plurality of channels of the multiphase DC-DC converter according to a plurality of current sensing signals of the plurality of channels, a time shift circuit, for adjusting pulse widths of a plurality of clock signals according to the plurality of current balance signals, and a ramp generator, for deciding shift levels of a plurality of ramp signals according to the plurality of clock signals.

The invention relates to the field of digital-analog hybrid integrated circuit design, aims to increase the conversion rate of a monoclinic ADC and provides the analog-digital converter which is simple in structure and low in power consumption. According to the adopted technical scheme of a low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and a converter, the converter is composed of a ramp generator, a counter, comparators, multiplexer switches and a register; the ramp generator generates a ramp voltage Vramp and k reference voltages VrefK, wherein K=1, 2, 3..., K; each of the k reference voltages VrefK is supplied to the corresponding comparator through one of the corresponding multiplexer switches; the ramp voltage Vramp is supplied to each comparator. The low-power consumption level multi-reference voltage monoclinic analog-digital conversion method and the converter are mainly applied to digital-analog hybrid integrated circuit design.

A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.

The invention is directed to an amplifier circuit based on the principle of a class D amplifier. To avoid unwanted convolution effects and to improve the power supply rejection ratio, provision is made for the amplitude of the ramp signal used for pulse width modulation to track proportionally the supply voltage for the amplifier circuit. For this purpose, the ramp signal generator has an amplitude control input suitably connected to supply and reference potentials. This ensures a constant duty ratio which is independent of the supply voltage. The present circuit may be used, for example, as a DC / DC converter or as an audio amplifier.

Methods and structures for ensuring the highly linear discharge of a capacitor used for slew rate control of a power driving stage from a maximum voltage to a minimum supply voltage, such as ground. A voltage ramp generator uses a single cascoded current source to achieve the linear ramp-down.

A control system that can accommodate the wide variations in the output of a generator, such as a permanent magnet alternator, while providing an output with relatively uniform phase ripple. The control system includes a zero crossing detector and variable ramp generator for generating control signals to a switching rectifier to generate a regulated DC signal.

A one cycle power factor correction converter circuit comprising a switch for controlling a DC output voltage of the converter circuit, the switch being switched by a drive signal having a frequency determined by a clock signal; the converter circuit being provided with a DC input voltage and producing the DC output voltage, the DC input voltage being rectified from an AC input; a controller circuit for controlling an on-time or off-time of the switch to set the output voltage and to achieve power factor correction at the AC input; the controller circuit comprising an error amplifier receiving a feedback voltage from the output of the converter circuit and a reference voltage and producing an error signal; a ramp generator receiving the error signal and generating a first ramp signal by integrating a signal related to the error signal; a pulse width modulation circuit receiving the first ramp signal and a signal related to the error signal and producing a pulse width modulated signal by comparing the first ramp signal and the signal related to the error signal; the pulse width modulated signal determining the on-time or off-time of the switch to control the output voltage with power factor correction; further comprising a circuit for terminating the first ramp signal when a predetermined inequality exists between the first ramp signal and a reference signal and for developing the clock signal from the first ramp signal.

A multi-phase DC-DC power converter including a pulse width modulation (PWM) controller and a plurality of output stage circuits is provided. The output stage circuits convert an input voltage into an output voltage. The PWM controller includes a PWM generation module, a ramp generator and a feedback circuit. The feedback circuit generates a trigger signal according to the output voltage and a ramp signal. The PWM generation module generates a PWM signal with a constant on time, and adjusts a duty cycle of the PWM signal according to the trigger signal, the input and output voltages, so as to control phase channels of the multi-phase DC-DC power converter in order.

The present invention relates to radio transmission of bursts in for example a TDMA cellular radio system. The burst starts with a ramping up period, ends with a corresponding ramping down ramping down period and with the pay-load information therebetween. The ramp form is created in a ramp generator (13) which gives a multiplication value to multiply the digital information to be transmitted in multipliers (15, 16). The multiplied values are converted into analogue form and amplified before being transferred to the antenna (21). Output power and temperature of the transmitting equipment are measured (22, 23) and used to update the output power levels during the next burst.

The invention discloses a column parallel analog-to-digital converter, a pixel photosensitive value output method and a CMOS image sensor. The column parallel analog-to-digital converter comprises a ramp generator, a counting unit and multiple column analog-to-digital converters, each column analog-to-digital converter corresponds to one row of pixel units of a pixel array and comprises a comparison processing unit and a storage unit, and each comparison processing unit comprises a capacitor, a switching module and a comparator. The column parallel analog-to-digital converter can shorten analog-to-digital conversion time and improve conversion efficiency.

A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective voltage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp. A respective local ramp generating circuit is provided for each array sector and for the array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.

An application-specific embeddable flash memory having three content-specific I / O ports and delivering a peak read throughput of 1.2 GB / s. The memory is combined with a special automatic programming gate voltage ramp generator circuit having a programming rate of 1 Mbyte / s for non-volatile storage of code, data, and embedded FPGA bit stream configurations. The test chip uses a NOR-type 0.18 μm flash embedded technology with 1.8V power supply, two poly, six metal and memory cell size of 0.35 μm2.