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2318 results about "Flip-flop" patented technology

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information – a bistable multivibrator. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are fundamental building blocks of digital electronics systems used in computers, communications, and many other types of systems.

Multi-stage memory buffer and automatic transfers in vehicle event recording systems

Vehicle event recorder systems are arranged with three stage memories and special mechanism to manage those memories including transfer of data there between. Namely, a managed loop memory receives data from a video camera in real-time and continuously overwrites expired data implicitly determined no longer useful. Data in a managed loop memory is only passed to a more stable memory, a high-capacity buffer memory, in response to an event having occurred. An event trigger produces a signal, which causes data transfer between the managed loop memory and an on-board, high-capacity buffer memory. The high-capacity buffer memory is suitable for storing video series associated with a plurality of events. Finally, a permanent data store is arranged to receive data from the high-capacity buffer memory whenever the system returns and falls within a predetermined proximity of a download station.
Owner:SMARTDRIVE SYSTEMS

Triggering applications based on a captured text in a mixed media environment

A Mixed Media Reality (MMR) system and associated techniques are disclosed. The MMR system provides mechanisms for forming a mixed media document that includes media of at least two types (e.g., printed paper as a first medium and digital content and / or web link as a second medium). In one particular embodiment, the MMR system includes an action processor and method, and MMR documents with an associated action. The MMR document structure is particularly advantageous because the ability to specify different actions for different MMR documents, combined with the ability to create any number of MMR documents for a particular location on any media, allows the MMR architecture to serve as a universal trigger or initiator for additional processing. In other words, addition processing or actions can be triggered or initiated based on MMR recognition. The action processor receives the output of the MMR recognition process which yields an MMR document including at least one action. The action processor executes that action which includes various commands to the MMR system or other systems coupled to the MMR system. The MMR system architecture is advantageous because an action can be executed by pointing the capture device at a block of text, and the action is performed. Example actions include retrieving the text in electronic form to the capture device, retrieving the specification for the action, inserting data to a MMR document, transferring data between documents, purchasing items, authoring actions or reviewing historical information about actions. The MMR system includes a variety of user applications (one or more actions) initiated by the MMR recognition of a text patch such as information retrieval for a travel guide book, stock listings or advertisements; information capture such as recording content from a conference, recording and storing multimedia associated with the document, capturing information for a calendar and on the fly authoring; purchasing media files for storage on any part of an MMR document.
Owner:RICOH KK

Methods and apparatus for advanced recording options on a personal versatile recorder

Advanced recording options are provided on a personal versatile recorder (PVR) or similar recording device. Television signals and associated electronic programming guide (EPG) data are received at a receiver (30). Recorded program material is stored in a storage device (60). A processor (75) provides for automatic suspending of recording, based on predetermined criteria, for at least a portion of time during which the one or more television programs would otherwise be recorded. Recording may be suspended when non-programming specific content (e.g., a commercial or emergency broadcast) is received at the PVR (20). Non-program specific content can be identified through the use of EPG data or Advanced Television Enhancement Forum (ATVEF) triggers. End of program notifiers may be provided which enable the PVR (20) to record the entire program, regardless of whether the program runs beyond its scheduled time. Recording may be optionally suspended where the program is a rerun.
Owner:GOOGLE TECH HLDG LLC

SRAM type FPGA single particle irradiation test system and method

ActiveCN103744014ARefresh is convenient and reliableReliably flip dataElectrical testingCommunication interfacePower flow
The invention provides an SRAM type FPGA single particle irradiation test system and method. The test system comprises a host computer, a current monitoring acquisition plate and a test plate. The current monitoring acquisition plate comprises a current monitoring acquisition FPGA, a current acquisition unit, a power supply module and a first communication interface; the test plate comprises a control processing FPGA, a refreshing chip, an SRAM, a configuration PROM, a storage PROM, a second communication interface and a detected FPGA; the host computer is in charge of flow control and data processing; the current monitoring acquisition plate is in charge of power-on and power-off of the test plate and monitoring and testing of FPGA currents; and the test plate is in charge of processing a command sent by the host computer and performing work such as single particle overturning, single particle function interruption detection and the like. According to the invention, the refreshing chip is utilized to replace some of the reconfiguration modules in a conventional irradiation test system so that a detected chip can be more conveniently and reliably refreshed; and the system and method provided by the invention can realize static and dynamic overturning testing on a trigger, and more reliable trigger overturning data can be obtained by combing the two methods.
Owner:BEIJING MICROELECTRONICS TECH INST +1

Low-power dissipation RS latch unit and low-power dissipation master-slave D flip-flop

InactiveCN101777907ASimple and completely symmetrical structureGood leakage power suppression performanceElectric pulse generatorLogic circuitsHemt circuitsControl theory
The invention discloses a low-power dissipation RS latch unit and a low-power dissipation master-slave D flip-flop, which is characterized in that the low-power dissipation RS latch unit comprises an input driving and synchronizing circuit, a pull-down circuit, a function control circuit, a first phase inverter and a second phase inverter, wherein the first phase inverter and the second phase inverter are mutually overlapped and coupled. The low power dissipation master-slave D flip-flop is composed of an input phase inverter, a clock phase inverter, a first low-power dissipation RS latch unit and a second low-power dissipation RS latch unit, wherein the first low power dissipation RS latch unit and the second low power dissipation RS latch unit have the same inner structure and are cascaded. The low power dissipation master-slave D flip-flop has the advantages that the low-power dissipation RS latch units use three kinds of leaked power consumption lowering technology, i.e. P-type logic technology, function control technology and double-threshold technology, so that the low-power dissipation RS latch units have better leaked power consumption inhibiting performance. The low-power dissipation master-slave D flip-flop has simple and totally symmetrical circuit structure. Compared with the traditional single-threshold transmission gate D trigger circuit, the invention can save 80% of leaked power consumption and 40% of total power consumption in the 90 nm process, so that the invention is suitable to serve as a digital circuit unit to the design of low-power consumption integrated circuits in the deep sub-micron CMOS process.
Owner:NINGBO UNIV

Data increment extraction method based on trigger

InactiveCN101923566AHigh degree of reusabilityHigh data extraction performanceSpecial data processing applicationsFlip-flopReal-time computing
The invention relates to the technical field of data processing, in particular to a data increment extraction method based on a trigger. The method accurately captures variable data in a business system according to certain frequency; meanwhile too big pressure is prevented from being acted on the business system so as to avoid affecting the existing business. Meanwhile, a user can extract incremental data generated in the current period from a resource system according to certain period in the mode of customizing a plan task, or real-time data synchronization capability can be realized in the mode of detecting variable data in real time, which is provided by the system. The invention has the beneficial effects that the invention provides a variable data capturing mechanism, i.e. the mechanism can ensure that new data and old data can be distinguished when the data resource data changes; and thus the invention extracts the data in an incremental mode and does not need to carry out total-amount amount extraction for keeping data synchronous.
Owner:浙江协同数据系统有限公司

High-precision method and device for measuring interval between positive time and negative time

The invention provides a high-precision method and device for measuring an interval between positive time and negative time. The device comprises a signal shaping and measuring gate extracting unit, a synchronization and interpolation unit, a clock counting unit, a storage unit and a data processing unit, wherein the signal shaping and measuring gate extracting unit, the synchronization and interpolation unit, the clock counting unit, the storage unit and the data processing unit are in connection with one another and in communication with one another. The signal shaping and measuring gate extracting unit conducts comparing and shaping on input signals according to a trigger level, converts measured signals into ECL level signals, and extracts gate signals corresponding to the measured signals through an ECL trigger. The synchronization and interpolation unit samples the two routes of gate signals through a counting clock. By means of the scheme, various types of signal input can be achieved, and the wide input dynamic range can be supported; a channel circuit is obtained through a high-speed ECL device, the channel bandwidth is large, narrow-pulse measurement can be achieved, the minimum measurable pulse width can reach 2.5ns, and the measurement resolution ratio can reach 40ps.
Owner:THE 41ST INST OF CHINA ELECTRONICS TECH GRP

Systolic linear-array modular multiplier with pipeline processing elements

A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 mu m CMOS technology, a clock signal up to 180 MHz can be used. In average, for n-bit modular multiplication, the encryption speed can reach 116 Kbit / s (kilobits per second), which is substantially twice that achieved by the prior art.
Owner:UNITED MICROELECTRONICS CORP

Gaming machine using multiple triggers to determine an award from a subset of displayed awards

A gaming system includes at least one input device adapted to receive a physical item associated with a monetary value that establishes a credit balance, an input indicative of a wager drawn on the credit balance for a wagering game, and a cashout input that initiates a payout from the credit balance. In response to a wager input, a wagering game is initiated that includes the spinning and stopping of a set of bonus reels through a plurality of bonus spins populating a bonus array with bonus symbols. The bonus reels comprise a combination of symbols reducing display processing requirements and improve mapping random numbers to displayed symbols for display during bonus spins having reduced durations. When completed, an award is determined based according to values associated with less than all of the bonus symbols displayed in a bonus outcome array.
Owner:LNW GAMING INC

Method and device for measuring time interval through delay line in cascaded two stages

A method for measuring time interval with two stage cascade delay line includes measuring numbers of clock leading edge in time interval to be measured i e cycle number of clock, measuring two time intervals not being complete cycle of front and back time intervals to be measured, sending those less than resolution of first stage relay line to the second stage for further subdivision, calculating out value of time interval to be measured by utilizing measured results. The measuring device is composed of only delay unit and D trigger for both delay lines.
Owner:TSINGHUA UNIV

Mobile barcode scanner gun system with mobile tablet device having a mobile Pos and enterprise resource planning application for customer checkout/order fulfillment and real time in store inventory management for retail establishment

A mobile scanner gun system efficiently and reliably processes a retail store purchase and / or performs daily store inventory management functions. The system has a main body portion extending toward a handle portion, the main body portion having a base, side walls, a front wall and a back wall constructed to form an interior cavity, wherein the front wall includes an aperture with a lens recessed therein. The front wall has a trigger member located near the base of the main body. A USB scanner input device is mounted above and in front of the trigger, the scanner having two drivers, including 1) a native device driver and 2) a keyboard input driver, the scanner device being in communication with the trigger for initiating a scan of a barcode. A USB MSR input device is integrated on the short edge of the mobile tablet device (upper receiver) and is used for processing payment card sales transactions through a secured PCI compliant, end to end encrypted bank card processor. The top wall of the main body portion includes an attachment means comprising a base mount universal receiver with rotational coupling means and a specialized universal serial bus wiring harness adapted to interchangeably mount and communicate with a mobile tablet device having a system integrated therein that enables real-time store level inventory management and a fully functioning POS capability for selling merchandise in a retail sales environment. The base mount universal receiver with rotational coupling allows the mobile tablet device to rotate from portrait mode to landscape mode without operational delay of the system.
Owner:RETAIL TECH

Automatic fluid channel screen lock-unlock system

The present invention relates to a screen lock-unlock system for automatically locking and unlocking a screen that is within a fluid channel wherein the screen is rotatable relative to the channel from closed to open. The system includes an actuator comprising a flapper and a trigger, wherein the flapper is rotatably connectable to the back of the screen. The flapper is operably connected to the trigger for moving the trigger. And, the system is further summarized, according to one aspect, as follows. It includes a lock bar wherein the lock bar is rotatably attachable to a screen support structure, the lock bar being rotatable by movement of the trigger. The lock bar intercepts the rearward arc path of a blockable part (such as a flange extending laterally from the screen). The flapper is located and oriented with respect to the closed screen for at least part of the flapper to be rotatable in response to pressure from impact fluid. The trigger is located sufficiently close to the lock bar for rotation of the trigger to move the lock bar in a direction and amount needed for at least part of the lock bar to clear the blockable part, allowing the screen to open in response to pressure against the front of the screen. The screen is rotatable toward a closed position in response to the diminishment of the pressure against the front of the screen. And, the lock bar is biased in a counter-rotation direction (by part of the lock bar and / or another biasing device) to at least help hold the lock bar in and / or return it to a locked position.
Owner:NINO KHALIL IBRAHIM

High-precision TDC based on equivalent segmentation and equivalent measurement method thereof

The invention discloses a high-precision TDC based on equivalent segmentation. A second-order time digital conversion structure of equivalent segmentation based on an FPGA is adopted, and the high-precision TDC comprises a first-order delay ring reduction interpolator, a second-order interpolator based on equivalent segmentation, a triggering pulse generation module, a synchronization module, an integer period counter, a data storage module and a delay line phase-locked oscillator. According to the first-order interpolator, the conversion rate of the TDC is increased with a low measurement resolution ratio, the second-order interpolator is composed of multiple delay ring reduction interpolators connected in parallel, by the adoption of an equivalent segmentation method, the measurement resolution ratio is increased, measurement precision is improved, the triggering pulse generation module is used for generating a starting signal and an ending signal for the TDC, the synchronization module eliminates the semi-stable state effect of a register through multiple trigger structures, the integer period counter is composed of multiple counters based on the principle of the shifting register, and the delay line phase-locked oscillator uses feedback for controlling core voltage of the FPGA to stabilize the measurement result of the TDC. The measurement prevision is high, and the conversion rate is high.
Owner:INNOVATION ACAD FOR PRECISION MEASUREMENT SCI & TECH CAS +1
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