2327 results about "Flip-flop" patented technology

Vehicle event recorder systems are arranged with three stage memories and special mechanism to manage those memories including transfer of data there between. Namely, a managed loop memory receives data from a video camera in real-time and continuously overwrites expired data implicitly determined no longer useful. Data in a managed loop memory is only passed to a more stable memory, a high-capacity buffer memory, in response to an event having occurred. An event trigger produces a signal, which causes data transfer between the managed loop memory and an on-board, high-capacity buffer memory. The high-capacity buffer memory is suitable for storing video series associated with a plurality of events. Finally, a permanent data store is arranged to receive data from the high-capacity buffer memory whenever the system returns and falls within a predetermined proximity of a download station.

A Mixed Media Reality (MMR) system and associated techniques are disclosed. The MMR system provides mechanisms for forming a mixed media document that includes media of at least two types (e.g., printed paper as a first medium and digital content and / or web link as a second medium). In one particular embodiment, the MMR system includes an action processor and method, and MMR documents with an associated action. The MMR document structure is particularly advantageous because the ability to specify different actions for different MMR documents, combined with the ability to create any number of MMR documents for a particular location on any media, allows the MMR architecture to serve as a universal trigger or initiator for additional processing. In other words, addition processing or actions can be triggered or initiated based on MMR recognition. The action processor receives the output of the MMR recognition process which yields an MMR document including at least one action. The action processor executes that action which includes various commands to the MMR system or other systems coupled to the MMR system. The MMR system architecture is advantageous because an action can be executed by pointing the capture device at a block of text, and the action is performed. Example actions include retrieving the text in electronic form to the capture device, retrieving the specification for the action, inserting data to a MMR document, transferring data between documents, purchasing items, authoring actions or reviewing historical information about actions. The MMR system includes a variety of user applications (one or more actions) initiated by the MMR recognition of a text patch such as information retrieval for a travel guide book, stock listings or advertisements; information capture such as recording content from a conference, recording and storing multimedia associated with the document, capturing information for a calendar and on the fly authoring; purchasing media files for storage on any part of an MMR document.

Methods and systems for an automated dialer enhancements. The methods may analyze transactions. The analysis of the transactions may comprise of triggers which are met when a delta threshold is exceeded, when an immediate threshold is exceeded, or when a rule is met. A notification strategy is implemented after a trigger is fired and accounts may be blocked or held. Reappearing transactions are flagged and escalated.

Advanced recording options are provided on a personal versatile recorder (PVR) or similar recording device. Television signals and associated electronic programming guide (EPG) data are received at a receiver (30). Recorded program material is stored in a storage device (60). A processor (75) provides for automatic suspending of recording, based on predetermined criteria, for at least a portion of time during which the one or more television programs would otherwise be recorded. Recording may be suspended when non-programming specific content (e.g., a commercial or emergency broadcast) is received at the PVR (20). Non-program specific content can be identified through the use of EPG data or Advanced Television Enhancement Forum (ATVEF) triggers. End of program notifiers may be provided which enable the PVR (20) to record the entire program, regardless of whether the program runs beyond its scheduled time. Recording may be optionally suspended where the program is a rerun.

The invention relates to the technical field of data processing, in particular to a data increment extraction method based on a trigger. The method accurately captures variable data in a business system according to certain frequency; meanwhile too big pressure is prevented from being acted on the business system so as to avoid affecting the existing business. Meanwhile, a user can extract incremental data generated in the current period from a resource system according to certain period in the mode of customizing a plan task, or real-time data synchronization capability can be realized in the mode of detecting variable data in real time, which is provided by the system. The invention has the beneficial effects that the invention provides a variable data capturing mechanism, i.e. the mechanism can ensure that new data and old data can be distinguished when the data resource data changes; and thus the invention extracts the data in an incremental mode and does not need to carry out total-amount amount extraction for keeping data synchronous.

A systolic linear-array modular multiplier is provided, which can perform the modular multiplication algorithm of P. L. Montgomery more efficiently. The total execution time for n-bit modular multiplication is 2n+11 cycles. The modular multiplier includes a linear array of processing elements which is constructed based on a pipeline architecture that can reduce the computation procedure by one clock period. Each of the processing elements is simple in structure, which is composed of four full adders and fourteen flip-flops. For n-bit modular multiplication, a total number of 46n+184 gates is required, which is substantially less as compared to the prior art, so that manufacturing cost of the modular multiplier can be significantly reduced. These features make the modular multiplier suitable for use in VLSI implementation of modular exponentiation which is the kernel computation in many public-key cryptosystems, such as the RSA (Rivest-Shamir-Adleman) system. With the 0.8 mu m CMOS technology, a clock signal up to 180 MHz can be used. In average, for n-bit modular multiplication, the encryption speed can reach 116 Kbit / s (kilobits per second), which is substantially twice that achieved by the prior art.

A gaming system includes at least one input device adapted to receive a physical item associated with a monetary value that establishes a credit balance, an input indicative of a wager drawn on the credit balance for a wagering game, and a cashout input that initiates a payout from the credit balance. In response to a wager input, a wagering game is initiated that includes the spinning and stopping of a set of bonus reels through a plurality of bonus spins populating a bonus array with bonus symbols. The bonus reels comprise a combination of symbols reducing display processing requirements and improve mapping random numbers to displayed symbols for display during bonus spins having reduced durations. When completed, an award is determined based according to values associated with less than all of the bonus symbols displayed in a bonus outcome array.

Some embodiments of the invention provide a configurable integrated circuit (“IC”). The configurable IC includes a set of configurable logic circuits for configurably performing a set of functions. The configurable IC also includes a set of configurable routing circuits for routing signals to and from the configurable circuits. During several operational cycles of the configurable IC, a set of data registers are defined by the configurable routing circuits. These data registers may be used wherever a flip-flop can be used.

A method for measuring time interval with two stage cascade delay line includes measuring numbers of clock leading edge in time interval to be measured i e cycle number of clock, measuring two time intervals not being complete cycle of front and back time intervals to be measured, sending those less than resolution of first stage relay line to the second stage for further subdivision, calculating out value of time interval to be measured by utilizing measured results. The measuring device is composed of only delay unit and D trigger for both delay lines.

The present invention relates to a time digital converter, and more particularly, to a noise-shaping time to digital converter (TDC) that has a 1-bit output and uses a delta-sigma modulation method. The noise-shaping time to digital converter (TDC) that has the 1-bit output and uses the delta-sigma modulation method in accordance with the present invention eliminates the need for a large number of D flip-flops or counters and a plurality of delay units connected in series to one another because the time to digital converter is fabricated such that a delay element has a resolution of the effective delay time in a semiconductor process, unlike the conventional time to digital converter. Therefore, the time to digital converter of the present invention has an advantage in that an extremely high resolution and high linearity can be achieved with an efficient circuit configuration and low power consumption.

A pistol-grip module includes a handle and a coupling member that is configured to couple, mechanically and electrically, to a battery compartment of an active frame. The active frame, which includes at least one electrically powered device, is intended to receive a data-capture device, such as a smart phone. In versions of the pistol-grip module that include a trigger, the trigger can be used to actuate the electrically powered device of the active frame.