Multi-threshold flip-flop circuit having an outside feedback
a flip-flop circuit and multi-threshold technology, applied in the field of flip-flop circuits and multi-threshold flip-flop circuits having an outside feedback, can solve the problems of circuits having significant increased complexity, low threshold voltage giving rise to a higher sub-threshold leakage current, and increasing the relative level of leakage currents
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[0014] Referring now to the drawings and in particular to FIG. 1, there is depicted a circuit diagram of a typical master-slave flip-flop circuit, according to the prior art. As shown, a flip-flop circuit 10 includes a master latch 11 and a slave latch 12. Flip-flop circuit 10 has two clock phases, namely, {umlaut over (l)}.dagger.1 and {umlaut over (l)}.dagger.2. Switches S1 and S2, which can be pass gates or pass transistors, are activated by clock phases {umlaut over (l)}.dagger.1 and {umlaut over (l)}.dagger.2, respectively. By convention, a switch is closed when the clock is at a logical high (i.e., a logical one), and the switch is opened when the clock is at a logical low (i.e., a logical zero). For flip-flop circuit 10 to function correctly, clock phases {umlaut over (l)}.dagger.1 and {umlaut over (l)}.dagger.2 need to be non-overlapping (i.e., off-phase with each other). When clock phase {umlaut over (l)}.dagger.1 is high, master latch 11 is transparent and slave latch 12 i...
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