2515 results about "Peak current" patented technology

An adaptive current limiter including a conversion network and an amplifier network developing an adaptive current limit signal for use by a switching regulator to limit peak current through an inductor of the switching regulator. The switching regulator develops a pulse control signal for controlling switching of current through the inductor to convert an input voltage to an output voltage. The conversion network provides a limit value by applying a duty cycle of the pulse control signal to a reference value. The amplifier network is configured to develop the adaptive current limit signal based on the limit value. The conversion network may multiply the reference value by the duty cycle to develop the limit value. The amplifier network may include a current source providing a fixed reference current to an amplifier to establish a minimum level of the adaptive current limit signal.

A direct current arc fault circuit interrupter includes separable contacts and a trip circuit to trip open the contacts. The trip circuit includes a number of alternating current sensors structured to sense a current flowing through the separable contacts, a number of filter circuits cooperating with the AC current sensors to output a number of AC signals, a number of peak detectors cooperating with the filter circuits to output a number of peak current signals, and a processor cooperating with at least the peak detectors. The processor inputs the number of peak current signals as a plurality of peak current signals or inputs the number of peak current signals and determines the plurality of peak current signals. The processor also determines if the peak current signals exceed corresponding predetermined thresholds for a predetermined time, and responsively causes the contacts to trip open.

A system drives one or plurality of LEDs regulating their brightness by controlling LEDs average current or voltage. The system includes a switching power converter and an integrated digital regulator with at least one of electrical, thermal and optical feedbacks. The regulator is constructed as a hysteretic peak current mode controller for continuous mode of operation of the power converter. For discontinuous mode of operation of the power converter a pulse averaging sliding mode control is being used. Average LED current is measured by integrating LED pulse current at off time and hysteretically adjusting on time of the power switch. Input battery is protected from discharging at abnormally low impedance of the output.

The present invention provides a method and apparatus for controlling the thermal stress in lighting devices, for example light-emitting elements, that are exposed to large thermal gradients typically upon start-up, for example light-emitting elements operating in relatively cold ambient environments. The present invention provides an apparatus that can reduce this thermal stress, wherein the apparatus comprises a temperature determination mechanism for evaluating the temperature of the light-emitting elements prior to activation, and a control system to control the drive current such that it is gradually ramped up to the desired steady state peak current value, wherein the ramping of the drive current is dependent on the evaluated temperature of the light-emitting element.

Detection of abnormal signal traces in electrochemical measurements generated using an electrochemical test strip to which a potential is applied allows for an indication of an erroneous analyte determination. The current trace has an expected shape in which a peak current is observed a time tpeak after which there is a decrease in current. To detect abnormal signal traces, the time tpeak is determined experimentally and compared with an expected value, t′peak, and if the difference between the two values to over a predetermined threshold, an error message is provided to the user instead of a test result. The value of t′peak is determined as a function of a mobility term that is determined during a potentiometry phase following the amperometric measurements.

A solid-state light engine comprised of light emitting diodes (LEDs) configured into a bridge rectifier with a current limiting module coupled to the LED bridge rectifier. The light engine may be packaged for high temperature operation. Optionally, the LEDs comprise wavelength-converting phosphors with a persistence that is a multiple of the peak to peak current period, to smooth and mask ripple frequency pulsation of emitted light.

A circuit that utilizes most of the energy stored in the bulk capacitor of an AC to DC or DC to DC converter power supply by providing an intermediate converter between a first stage boost converter and a DC-DC converter. When the bulk voltage starts to fall during the hold-up time, the intermediate converter boosts the falling voltage to maintain the regulated DC input to the DC to DC converter while reducing the operating range and increasing the operating duty cycle, so as to increase efficiency, reduce peak current and voltage stresses. The circuit also reduces the size of the output filter components and reduces the size of the bulk capacitance by up to half.

A parallel compression test circuit of a memory device disperses peak current and reduce noise by operating input / output amplifiers at different timings in a parallel compression test mode. The parallel compression test circuit comprises an input / output amplification control unit for activating a plurality of input / output amplifiers connected to a selected bank in a normal mode, and activating the plurality of input / output amplifiers in each bank at different timings in a test mode.

A wake-up circuit of a memory device employs a cascade chain structure in which bit lines are divided into a plurality of blocks, and if the bit lines of one of the blocks are determined to have undergone a wake-up operation based on a bit line voltage fed back in the block, the wake-up operation is performed on a subsequent block. Accordingly, a wake-up delay can be varied, and therefore peak currents can be controlled, thereby reducing overall system power noise.

An apparatus and method thereof for measuring an output current from a primary side of a power converter are provided. A peak detector is designed to sample a peak value of a converted voltage of a primary-side switching current. A zero-current detector detects a discharge-time of a secondary-side switching current through an auxiliary winding of a transformer. An oscillator generates a switching signal for switching the power converter. An integrator generates an integrated signal by integrating the converted voltage of the primary-side switching peak current with the discharge-time. The time constant of the integrator is correlated with the switching period of the switching signal. The integrated signal is thus proportional to the output current of the power converter.

A circuit interrupter includes band pass filters cooperating with a current sensor to output bands having different, non-overlapping ranges of frequencies, peak detectors cooperating with the filters to detect corresponding peak current values, envelope detectors cooperating with the filters to detect corresponding occurrences from the bands being within corresponding predetermined magnitude ranges, a counter counting the occurrences, and a processor providing and disabling series arc detection when sensed current is greater than a first predetermined value. The processor determines tallies responsive to peak current values exceeding corresponding thresholds, determines series arcing from sensed current being less than the first predetermined value for a predetermined time, the tally for a current half-cycle being nonzero, and a count for the current half-cycle being different than the count for an immediately previous half-cycle of like polarity by at least a second predetermined value. A series chaos accumulator is increased responsive to series arcing.

The disclosure relates to a memory such as a DRAM (dynamic random access memory), specifically to a refresh controller embedded in a memory. The refresh controller according to the present invention lowers the levels of peak currents by differentiating active times of a first bank enable signal and a second bank enable signal. The present invention has an advantage that there is no problem of substantially reducing a refresh prosecution time for a second portion because a delayed refresh enable signal is being disabled even while the second bank enable signal is being enabled.

Apparatus and method for generating controlled-linewidth laser-seed-signals for high-powered fiber-laser amplifier systems. In some embodiments, the natural chirp (frequency change of laser light over a short start-up time) of a DBR laser diode when driven by pulsed current is used to broaden the linewidth of the laser output, while adjusting the peak current and / or the pulse duration to obtain the desired linewidth.

A pulsed waveform welding operation is implemented by reference to a commanded wire feed speed set by an operator. The wire feed speed is set on a wire feeder, and a signal representative of the commanded wire feed speed is applied to a power supply. The power supply control circuitry references a look-up table in which pulsed waveform parameters are provided based upon wire feed speed. The parameters may include multiple parameters such as pulse frequency, peak current, background current, and current ramp rates. The control circuitry commands power conversion circuitry to generate the commanded waveform as a function of the commanded wire feed speed.