101 results about "Common collector" patented technology

An electrostatic discharge (ESD) protection device (41, 51, 61, 71, 81) coupled across input-output (I / O) (22) and common (23) terminals of a core circuit (24) that it is intended to protect from ESD events, comprises, one or more serially coupled resistor triggered ESD clamp stages (41, 41′, 41″; 71, 71′, 71″), each stage (41, 41′, 41″; 71, 71′, 71″) comprising first (T1, T1′, T1″, etc.) and second transistors (T2, T2′, T2′″ etc.) having a common collector (52, 52′, 52″) and first (26, 26′, 26″) and second (36, 36′, 36″) emitters providing terminals (32, 42; 32′, 42′; 32″, 42″) of each clamp stage (41, 41′, 41″; 71, 71′, 71. A first emitter (25) of the first stage (41, 71) couples to the common terminal (23) and a second emitter (42″) of the last stage (41″, 71′) couples to the I / O terminals (22). Zener diode triggers are not used. Integrated external ESD trigger resistors (29, 29′, 29″; 39, 39′, 39″) (e.g., of poly SC) are coupled between the base (28, 28′, 28″; 38, 38′, 38″) and emitter (26, 26′, 26″; 36, 36′, 36″) of each transistor (T1, T1′, T1″; T2, T2′, T2″). Different resistor values (e.g., ˜0.5 k to 150 k Ohms) give different ESD trigger voltages. Cascading the clamp stages (41, 41′, 41″; 71, 71′) gives even higher trigger voltages. The ESD trigger resistances (29, 29′, 29″; 39, 39′, 39″) are desirably located outside the common collector-isolation wall (741, 742, 743; 741′, 742′, 743″) surrounding the transistors (T1, T1′, T1″; T2, T2′, T2″).

A semiconductor device having an improved voltage control oscillator circuit is provided. The voltage control oscillator circuit includes, in combination, a variable-capacitance element and at least one bipolar transistor on a single semiconductor substrate. The variable-capacitance element includes reversely serially connected PN junctions, and junctions are formed by a single common collector layer and separated base layers on the common collector layer. The capacitance of the variable-capacitance element is generated between respective base layers of the PN junctions with the common collector layer, and varies in correspondence with the voltage applied to the common collector layer.

A power semiconductor module has four power terminals. An IGBT has a collector connected to the first power terminal and an emitter coupled to the third power terminal. An anti-parallel diode is coupled in parallel with the IGBT. A DC-link is connected between the second and fourth power terminals. The DC-link may involve two diodes and two IGBTs, where the IGBTs are connected in a common collector configuration. The first and second power terminals are disposed in a first line along one side of the module, and the third and fourth power terminals are disposed in a second line along the opposite side of the module. Two identical instances of the module can be interconnected together to form a three-level NPC phase leg having low stray inductances, where the phase leg has two parallel DC-links.

A balanced crystal oscillator circuit comprising: a piezoelectric element Xtal (207; 215; 222,221; 313); a first oscillator subcircuit (202; 210; 218; 302) incorporating a transistor (204;212;220;304); and a second oscillator subcircuit (201;209;217; 301) incorporating a transistor (203; 211; 219; 303); wherein the transistors each have different types of transistor terminals (C,B,E; D;G;S), and wherein the oscillator subcircuits are configured with at least three interconnections. Each interconnection comprise a pair of like type of transistor terminals; wherein a first of said interconnections constitutes a connection to a ground reference (gnd); a second of said interconnections is via a first resonator element (207;215;223;313); and a third of said interconnections is via a second resonator element (208;216;224;314); said first and second circuits are arranged to interact by means of said first and second resonator elements to form a balanced oscillator signal. A dual common base or a dual common collector configuration is preferred.

Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.

A cell array is formed by a plurality of cells each including a selection bipolar transistor and a storage component. The cell array is formed in a body including a common collector region of P type; a plurality of base regions of N type, overlying the common collector region; a plurality of emitter regions of P type formed in the base regions; and a plurality of base contact regions of N type and a higher doping level than the base regions, formed in the base regions, wherein each base region is shared by at least two adjacent bipolar transistors.