3349 results about "Silicon-controlled rectifier" patented technology

Exemplary embodiments provide an impedance matching circuit for providing variable power from a dimmer switch having a triac to a switching power supply couplable to solid-state lighting. An exemplary impedance matching circuit includes a first resistor coupled to receive a first current from the switching power supply; a second resistor; and a transistor coupled in series to the second resistor, with the transistor responsive to a gate voltage to modulate a second current through the second resistor in response to a detected level of the first current through the first resistor.

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device.

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device

The invention relates to a low-temperature smoke denitration SCR (silicon controlled rectifier) catalyst, which comprises a carrier, a manganese oxide, and composite oxide of one or more of Ce, Zr, Ti, Co, Fe and Cu, the mass content of manganese is 0.1-66 percent, and the total mass content of the Ce, Zr, Ti, Co, Fe or/and Cu is 0-50 percent; and glass fiber and/or kieselguhr is used as the carrier, wherein the glass fiber of the carrier is calcined for 2-4 hours at temperature of 400-600 DEG C, then placed in a nitric acid, sulfuric acid or hydrochloric acid solution with mass concentration of 5-40 percent for acidizing for 1-8 hours, washed by distilled water to be neutered, dried at temperature of 80-120 DEG C, and crushed to have the fineness of 20-325 meshes. The catalyst uses the glass fiber and the kieselguhr as the carriers, so that the dispersion effect of nanoparticles and specific surface area of the catalyst are increased, the high adsorptive capacity and strong heat resistance and corrosion resistance capacity are achieved, stronger toxic resistance capacity to sulfur dioxide and stream contained in the smoke is realized, the invention can be used for 10-200 DEG C of low temperature smoke denitration, and has strong water resisting and sulphur toxic resisting capacities.

An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.

A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

The invention discloses a distributing net single phase earth fault type and a distinguishing method of phase identification, relating to a distributing net single phase earth fault distinguishing method in the field of AC distributing net testing and relaying protection technology. According to the invention, through collecting three-phase voltage of the distributing net system and neutral point voltage of the distributing net system, phase angle of each eigenvector is computed through a special relation, the type of the fault and the phase identification can be fast distinguished through the phase angle distinguishing logic. The inventive working system is that a three-phase bus (000), a grounding transformer (100), a linear side of an arc suppression coil (200) are connected in turn with the earth; a controller (400), a thyristor (300) and a secondary side of an arc suppression coil (200) are connected in turn. The invention is simple in criterion, small in collection quantity, fast in distinguishing speed, high in accuracy, reliable in security, which is suitable for 3-66 KV distributing net based on an aerial line or a power cable.

The invention relates to a sub-module circuit board used for a dynamic simulation test for simulating a high-capacity multi-level modular converter (MMC). A digital controller on the circuit board is used for controlling a plurality of MMC sub-modules of which parameters are reduced according to an exponential method, the sub-modules are connected in series. Each MMC sub-module comprises a main circuit an insulated gate bipolar transistor (IGBT) and silicon controlled rectifier driving circuit, a capacitance and voltage sampling circuit, a circuit board isolation power supply, a control and coding-decoding chip shared by a plurality of sub-modules, and a fiber channel, wherein the main circuit a capacitor, two IGBTs which are connected vertically in series and connected with the capacitor in parallel, a bypass switch connected with the lower IGBT in parallel, and a silicon controlled rectifier which is used for protecting the IGBTs and the capacitor and connected with the lower IGBT.

A light-adjusting and current-limiting control circuit for a lamp includes a sampling circuit formed of a manganese-copper line or a current transformer, a power circuit provided with resistors, capacitors, diodes, a Varistor and a zener diode, a signal adjusting circuit composed of diodes, resistors, a varistor, triacs and capacitors, and a control output circuit having a thyristor, diodes, a relay and an LED. The control output circuit can be replaced with a light-adjusting input circuit, a chip processor control circuit, a zero-crossing detection circuit and a two-way silicon controlled rectifier control output circuit 5. Thus, the invention has a low cost, a small size and an excellent precision, compared to conventional ones.

A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode. The anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material. The ESD protection circuit further includes an inductor electrically coupled between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material.

The invention provides a leakage detecting protection circuit capable of periodically automatically detecting function integrity. The leakage detecting protection circuit comprises a main loop switch, a resetting button, a tripping coil, a silicon controlled rectifier, an induction coil for detecting leakage current, a self-induction coil for detecting a low-resistance failure and a control chip which drives the switching-on/off of the silicon controlled rectifier by a leakage current detection result, and further comprises a) a timer for periodically outputting a function integrity detection signal, b) a detection signal latching circuit, c) an analogue test switch for generating analogue leakage current, d) a delay output circuit and e) a sampling circuit, wherein the timer outputs the detection signal to the latching circuit and the delay output circuit; and if a function is detected to fail, the delay output circuit outputs a tripping signal to switch the silicon controlled rectifier on, and the main loop switch is switched off. The leakage detecting protection circuit has the main advantages of periodically automatically detecting whether the leakage protection function of the circuit is integral or not without annual testing and avoiding tripping within the service life of the circuit, along with more convenience of use.