3364 results about "Silicon-controlled rectifier" patented technology

Exemplary embodiments provide an impedance matching circuit for providing variable power from a dimmer switch having a triac to a switching power supply couplable to solid-state lighting. An exemplary impedance matching circuit includes a first resistor coupled to receive a first current from the switching power supply; a second resistor; and a transistor coupled in series to the second resistor, with the transistor responsive to a gate voltage to modulate a second current through the second resistor in response to a detected level of the first current through the first resistor.

Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations. A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region. The memory cell is configured to store a first data state which corresponds to a first charge in the body region in a first configuration, and a second data state which corresponds to a second charge in the body region in a second configuration. The method includes: providing the memory cell storing one of the first and second data states; and applying a positive voltage to a substrate terminal connected to the substrate beneath the buried layer, wherein when the body region is in the first state, the body region turns on a silicon controlled rectifier device of the cell and current flows through the device to maintain configuration of the memory cell in the first memory state, and wherein when the memory cell is in the second state, the body region does not turn on the silicon controlled rectifier device, current does not flow, and a blocking operation results, causing the body to maintain the second memory state.

A method of maintaining the data state of a semiconductor dynamic random access memory cell is provided, wherein the memory cell comprises a substrate being made of a material having a first conductivity type selected from p-type conductivity type and n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type; a second region having the second conductivity type, the second region being spaced apart from the first region; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; and a gate positioned between the first and second regions and adjacent the body region.

A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.

High side driver circuitry for a defibrillator circuit employs respective capacitors connected to respective gates of silicon controlled rectifiers serving as high side switches. Applying a voltage pulse to a selected capacitor turns on the associated SCR. Positive turn-on of the high side SCRs is insured by inserting a constant current source into the low side activation current path at start-up.

A silicon-on-insulator (SOI) electrostatic discharge (ESD) protection device that can protect very sensitive thin gate oxides by limiting the power dissipation during the ESD event, which is best achieved by reducing the voltage drop across the active (protection) device during an ESD event. In one embodiment, the invention provides very low triggering and holding voltages. Furthermore, the SOI protection device of the present invention has low impedance and low power dissipation characteristics that reduce voltage build-up, and accordingly, enable designers to fabricate more area efficient protection device

The invention relates to a low-temperature smoke denitration SCR (silicon controlled rectifier) catalyst, which comprises a carrier, a manganese oxide, and composite oxide of one or more of Ce, Zr, Ti, Co, Fe and Cu, the mass content of manganese is 0.1-66 percent, and the total mass content of the Ce, Zr, Ti, Co, Fe or / and Cu is 0-50 percent; and glass fiber and / or kieselguhr is used as the carrier, wherein the glass fiber of the carrier is calcined for 2-4 hours at temperature of 400-600 DEG C, then placed in a nitric acid, sulfuric acid or hydrochloric acid solution with mass concentration of 5-40 percent for acidizing for 1-8 hours, washed by distilled water to be neutered, dried at temperature of 80-120 DEG C, and crushed to have the fineness of 20-325 meshes. The catalyst uses the glass fiber and the kieselguhr as the carriers, so that the dispersion effect of nanoparticles and specific surface area of the catalyst are increased, the high adsorptive capacity and strong heat resistance and corrosion resistance capacity are achieved, stronger toxic resistance capacity to sulfur dioxide and stream contained in the smoke is realized, the invention can be used for 10-200 DEG C of low temperature smoke denitration, and has strong water resisting and sulphur toxic resisting capacities.

A system for protecting a high-speed input / output pad of an integrated circuit. The system includes a preferably parasitic silicon controlled rectifier (SCR) and a triggering mechanism that preferably includes an NMOS triggering FET. The SCR includes an anode connected to the input / output pad and a trigger input. The anode and the trigger input form a reverse-biased junction that, during normal operation of the integrated circuit, isolates the triggering mechanism from the input / output pad when power is applied to the integrated circuit.

A lighting system includes a dimmer output voltage emulator to cause a power converter interface circuit to generate an emulated dimmer output voltage. In at least one embodiment, the emulated dimmer output voltage corresponds to an actual dimmer output voltage but is unaffected by non-idealities in the dimmer output voltage, such as premature shut-down of a triac-based dimmer. By generating an emulated dimmer output voltage, the energy delivered to a load, such as a lamp, corresponds to a dimming level setting.

An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. In one embodiment, the ESD protection circuit includes a pad adapted for connection to a first voltage source of a protected circuit node of the IC, and a silicon controlled rectifier (SCR) having an anode adapted for coupling to the first voltage source, and a cathode adapted for coupling to a second voltage source. At least one capacitive turn-on device respectively coupled between at least one of a first gate of the SCR and the first voltage source, and a second gate of the SCR and the second voltage source.

Switch devices, such as Silicon Controlled Rectifier (SCR), DIAC, or TRIAC, on a semiconductor body are disclosed. P / N junctions can be built on a semiconductor body, such as polysilicon or active region body on an insulated substrate, with a first implant in one end and a second implant in the other end. The first and second implant regions are separated with a space. A silicide block layer can cover the space and overlap into both implant regions to construct P / N junctions in the interface.

An electrostatic discharge (ESD) protection device having high holding current for latch-up immunity. The ESD protection circuit is formed in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection device includes a silicon controlled rectifier (SCR) coupled between a protected supply line of the IC and ground. A trigger device is coupled from the supply line to a first gate of the SCR, and a first substrate resistor is coupled between the first gate and ground. A first shunt resistor is coupled between the first gate and ground, wherein the shunt resistor has a resistance value lower than the substrate resistor.

A semiconductor device for ESD protection of an input / output pad (301) of an integrated circuit built in a substrate of a first conductivity type comprising a multi-finger MOS transistor (304), its source (304b) and its gate (304c) connected to ground potential and its drain (304a) connected to the I / O pad. A well of the opposite conductivity type, partially separated from the substrate by shallow trench isolations, has a diode (302), its anode (302b) connected to the pad and also to the transistor drain, and its cathode (302a) connected to power 303). These transistor and diode connections create a parasitic silicon controlled rectifier (SCR) with the SCR-anode (310a) formed by the diode anode, the first base region formed by the well, the second base region formed by the substrate, and the SCR-cathode (311a) formed by the transistor source. The SCR structure provides a significantly lower clamping voltage and an about two times higher failure current than a substrate-pumped MOS transistor.

A stepped dimming ballast comprising a filter and rectifier circuit (1), a DC high voltage stabilizing circuit (2), a frequency control and switch circuit (3), a load current feedback circuit (5), a voltage signal processing circuit (6) and a voltage signal sampling circuit (7). The present invention is adapted for use in conjunction with a silicon controlled rectifier dimmer and / or a regular light switch whereby it is novel in structure and able to effect dimming in two predetermined and reliable operation modes.

The invention provides a design method of an LED (light-emitting diode) dimming driving switching power supply applied to various traditional dimmers. According to the design method, the LED driving power supply achieves the resistive load input-output characteristics similar to those of an incandescent light bulb, so that LED lights (semiconductor LEDs) can be well suitable for dimming of the traditional dimmers (including traditional dimmers adjusting the phases of conduction angles through leading edge phase cut and traditional dimmers adjusting the phases of conduction angles through trailing edge phase cut, wherein silicon controlled dimmers are dimmers adjusting the phases of conduction angles through leading edge phase cut) and be used in indoor places where the traditional dimmers are needed for dimming. The LED dimming driving switching power supply designed according to the design method provided by the invention comprises a dimmer starting circuit loop, a rectifying circuit, a phase detection and isolation circuit, a phase cut detection circuit, a power-factor correction circuit, a switching power supply circuit and an LED current control circuit.

A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

The invention discloses a distributing net single phase earth fault type and a distinguishing method of phase identification, relating to a distributing net single phase earth fault distinguishing method in the field of AC distributing net testing and relaying protection technology. According to the invention, through collecting three-phase voltage of the distributing net system and neutral point voltage of the distributing net system, phase angle of each eigenvector is computed through a special relation, the type of the fault and the phase identification can be fast distinguished through the phase angle distinguishing logic. The inventive working system is that a three-phase bus (000), a grounding transformer (100), a linear side of an arc suppression coil (200) are connected in turn with the earth; a controller (400), a thyristor (300) and a secondary side of an arc suppression coil (200) are connected in turn. The invention is simple in criterion, small in collection quantity, fast in distinguishing speed, high in accuracy, reliable in security, which is suitable for 3-66 KV distributing net based on an aerial line or a power cable.

An ESD protection circuit is formed at the input / output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input / output interface contact of the integrated circuit and a power supply connection of the integrated circuit and a biasing circuit. The biasing circuit is connected to the polysilicon bounded SCR to bias the polysilicon bounded SCR to turn on more rapidly during the ESD event. The biasing circuit is formed by at least one polysilicon bounded diode and a first resistance. Other embodiments of the biasing circuit include a resistor / capacitor biasing circuit and a second diode triggering biasing circuit.

A system and method includes a controller that is configured to coordinate (i) a low impedance path for a dimmer current, (ii), control of switch mode power conversion and (iii) an inactive state to, for example, to allow a dimmer to function normally from cycle to cycle of an alternating current (AC) supply voltage. In at least one embodiment, the dimmer functions normally when the dimmer conducts at a correct phase angle indicated by a dimmer input setting and avoids prematurely resetting while conducting. In at least one embodiment, by coordinating functions (i), (ii), and (iii), the controller controls a power converter system that is compatible with a triac-based dimmer. In at least one embodiment, the controller coordinates functions (i), (ii), and (iii) in response to a particular dimming level indicated by a phase cut, rectified input voltage supplied to the power converter system.

A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.

The invention relates to a sub-module circuit board used for a dynamic simulation test for simulating a high-capacity multi-level modular converter (MMC). A digital controller on the circuit board is used for controlling a plurality of MMC sub-modules of which parameters are reduced according to an exponential method, the sub-modules are connected in series. Each MMC sub-module comprises a main circuit an insulated gate bipolar transistor (IGBT) and silicon controlled rectifier driving circuit, a capacitance and voltage sampling circuit, a circuit board isolation power supply, a control and coding-decoding chip shared by a plurality of sub-modules, and a fiber channel, wherein the main circuit a capacitor, two IGBTs which are connected vertically in series and connected with the capacitor in parallel, a bypass switch connected with the lower IGBT in parallel, and a silicon controlled rectifier which is used for protecting the IGBTs and the capacitor and connected with the lower IGBT.

A TRIAC / SCR-based energy savings device, system and method (1) wherein a predetermined amount of voltage below a nominal line voltage and / or below a nominal appliance voltage is saved, thereby conserving energy. Phase input connections (2) are provided for inputting analog signals into the device and system (1). A magnetic flux concentrator (3) senses the incoming analog signal (20) and a volts zero crossing point detector (5) determines the zero volts crossing point (21) of the signal (20). The positive half cycle (22) and negative half cycle (23) of the signal (20) are identified and routed to a digital signal processor (10) for processing the signal (20). The signal (20) is reduced by pulse width modulation and the reduced amount of energy is outputted, thereby yielding an energy savings for an end user.

Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source / drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

The invention discloses an LED driving circuit having a silicon controlled rectifier light modulator. A bleeder current of the silicon controlled rectifier light modulator at a conduction start stage in each AC period and a bleeder current after conduction and till being lightening of an LED load are distinguished, a bleeder circuit is controlled to bleed in a first relatively large current when the silicon controlled rectifier light modulator is at the conduction start stage, the bleeder circuit after conduction is controlled to bleed in a second relatively small current, an average bleeder current of the bleeder circuit in each period can be reduced, bleeder loss can be further reduced, and efficiency of the LED driving circuit is improved.

A bleeder circuit is provided in a switched mode power supply (SMPS) that provides a compensation current when the loop current drops below the holding current of the TRIAC to alleviate light flickering problem. Further, automatic power factor correction is also provided in embodiments of the invention, which enables the output current to be in phase with the input voltage. The power factor correction not only improves the efficiency of the power supply, it can also reduce the compensation current and the duration in which compensation current flows, thereby reducing the power loss in the bleeder circuit.

A lighting system includes a dimmer output voltage emulator to cause a power converter interface circuit to generate an emulated dimmer output voltage. In at least one embodiment, the emulated dimmer output voltage corresponds to an actual dimmer output voltage but is unaffected by non-idealities in the dimmer output voltage, such as premature shut-down of a triac-based dimmer. By generating an emulated dimmer output voltage, the energy delivered to a load, such as a lamp, corresponds to a dimming level setting.

A light-adjusting and current-limiting control circuit for a lamp includes a sampling circuit formed of a manganese-copper line or a current transformer, a power circuit provided with resistors, capacitors, diodes, a Varistor and a zener diode, a signal adjusting circuit composed of diodes, resistors, a varistor, triacs and capacitors, and a control output circuit having a thyristor, diodes, a relay and an LED. The control output circuit can be replaced with a light-adjusting input circuit, a chip processor control circuit, a zero-crossing detection circuit and a two-way silicon controlled rectifier control output circuit 5. Thus, the invention has a low cost, a small size and an excellent precision, compared to conventional ones.

A representative electrostatic discharge (ESD) protection circuit includes a silicon-controlled rectifier comprising an alternating arrangement of a first P-type semiconductor material, a first N-type semiconductor material, a second P-type semiconductor material and a second N-type semiconductor material electrically coupled between an anode and a cathode. The anode is electrically coupled to the first P-type semiconductor material and the cathode is electrically coupled to the second N-type semiconductor material. The ESD protection circuit further includes an inductor electrically coupled between the anode and the second P-type semiconductor material or between the cathode and the first N-type semiconductor material.

An electrostatic discharge (ESD) protection circuit in a semiconductor integrated circuit (IC) having protected circuitry. The ESD protection circuit includes a silicon controlled rectifier (SCR) having at least one first type high dopant region coupled to a first reference potential of the protected circuitry, and at least one second type high dopant region coupled to a second reference potential of the IC. The SCR is triggered by an external on-chip trigger device, which is adapted for injecting a trigger current into at least one gate of the SCR.