3007 results about "Insulated-gate bipolar transistor" patented technology

A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

In an IGBT with a built-in freewheeling diode, a thickness (D) of a polished wafer is equal to 200 μm or smaller, and each of respective thicknesses (T8) and (T9) of an N+-type cathode layer (8) and a P+-type collector layer (9) is equal to 2 μm or smaller. Further, a total width of the N+-type cathode layer (8) and the P+-type collector layer (9) which extends along a width direction (X) is in a range from 50 μm to 200 μm. In this case, an interface (IF2) between a collector electrode (10) and the P+-type collector layer (9) occupies 30-80% of an interface (IF) between the collector electrode (10) and the P+-type collector layer (9) plus the N+-type cathode layer (8).

The present invention generally relates to power electronic switching circuits and in particular to inverter modules employing two or more controlled switches that can be used with reactive loads. An inverter circuit is provided which comprises first and second input terminals for being connected to a DC power source; first and second output terminals for outputting an AC voltage; at least one metal oxide semiconductor field effect transistor, MOSFET, having a parasitic body diode. The inverter circuit further comprises at least one disabling element for disabling said body diode. This may result in an improved efficiency of the inverter circuit in combination with a reactive power capability. Further, a semiconductor switching device is disclosed, comprising at least one metal oxide semiconductor field effect transistor, MOSFET, and at least one insulated gate bipolar transistor, IGBT, wherein said MOSFET and said IGBT are connected in parallel.

To provide a reverse conducting semiconductor device in which an insulated gate bipolar transistor and a free wheeling diode excellent in recovery characteristic are monolithically formed on a substrate, the free wheeling diode including; a second conductive type base layer to constitute the insulated gate bipolar transistor; a first conductive type base layer for constituting the insulated gate bipolar transistor, an anode electrode which is an emitter electrode covering a first conductive type emitter layer and the second conductive type base layer, a cathode electrode which is a collector electrode covering the first conductive type base layer and a second conductive type collector layer formed on the part of the first conductive type base layer, wherein a short lifetime region is formed on a part of the first conductive type base layer.

A semiconductor device includes: a semiconductor substrate; a diode-built-in insulated-gate bipolar transistor having an insulated-gate bipolar transistor and a diode, which are disposed in the substrate, wherein the insulated-gate bipolar transistor includes a gate, and is driven with a driving signal input into the gate; and a feedback unit for detecting current passing through the diode. The driving signal is input from an external unit into the feedback unit. The feedback unit passes the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects no current through the diode, and the feedback unit stops passing the driving signal to the gate of the insulated-gate bipolar transistor when the feedback unit detects the current through the diode.

Double gate IGBT having both gates referred to a cathode in which a second gate is for controlling flow of hole current. In on-state, hole current can be largely suppressed. While during switching, hole current is allowed to flow through a second channel. Incorporating a depletion-mode p-channel MOSFET having a pre-formed hole channel that is turned ON when 0V or positive voltages below a specified threshold voltage are applied between second gate and cathode, negative voltages to the gate of p-channel are not used. Providing active control of holes amount that is collected in on-state by lowering base transport factor through increasing doping and width of n well or by reducing injection efficiency through decreasing doping of deep p well. Device includes at least anode, cathode, semiconductor substrate, n− drift region, first & second gates, n+ cathode region; p+ cathode short, deep p well, n well, and pre-formed hole channel.

There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

A semiconductor device includes a vertical IGBT and a vertical free-wheeling diode in a semiconductor substrate. A plurality of base regions is disposed at a first-surface side portion of the semiconductor substrate, and a plurality of collector regions and a plurality of cathode regions are alternately disposed in a second-surface side portion of the semiconductor substrate. The base regions include a plurality of regions where channels are provided when the vertical IGBT is in an operating state. The first-side portion of the semiconductor substrate include a plurality of IGBT regions each located between adjacent two of the channels, including one of the base regions electrically coupled with an emitter electrode, and being opposed to one of the cathode regions. The IGBT regions include a plurality of narrow regions and a plurality of wide regions.

An adaptive gate drive for an inverter includes control circuitry having a Field Programmable Gate Array (FPGA) and includes power circuitry having a plurality of FETs for operating a switching device, such as a Trench Gate Insulated Gate Bipolar Transistor (IGBT device). The control circuitry provides switching signals for operating the switching device. In addition, the control circuitry receives signals of output current of the IGBT device, temperature of the IGBT device, and DC link voltage. The FPGA has a plurality of operating points stored therein. Each operating point has corresponding parameters for a control signal that is used to control the turn-on or turn-off behavior of the IGBT device. During operation, the control circuitry compares the measured current, voltage and temperature operating points stored in the FPGA and sends the corresponding parameters to the gate drive circuit. The gate drive modifies the signal on the gate of the IGBT accordingly and thereby optimizes the turn-on and / or turn-off behavior of the device based on actual operating conditions.

An isolated bipolar transistor formed in a P-type semiconductor substrate includes an N-type submerged floor isolation region and a filled trench extending downward from the surface of the substrate to the floor isolation region. Together the floor isolation region and the filled trench form an isolated pocket of the substrate which contains the bipolar transistor. The collector of the bipolar transistor may comprise the floor isolation region. The substrate does not contain an epitaxial layer, thereby overcoming the many problems associated with fabricating the same.

This disclosure describes systems, methods, and apparatuses for impedance-matching radio frequency power transmitted from a radio frequency generator to a plasma load in a semiconductor processing chamber. Impedance-matching can be performed via a match network having a variable-reactance circuit. The variable-reactance circuit can comprise one or more reactive elements all connected to a first terminal and selectively shorted to a second terminal via a switch. The switch can comprise a bipolar junction transistor (BJT) or insulated gate bipolar transistor (IGBT) controlled via bias circuitry. In an on-state, the BJT base-emitter junction is forward biased, and AC is conducted between a collector terminal and a base terminal. Thus, AC passes through the BJT primarily from collector to base rather than from collector to emitter. Furthermore, the classic match network topology used with vacuum variable capacitors can be modified such that voltages do not overload the BJT's in the modified topology.

Connected to a 3-phase linear motor of a submersible oil pump of a crude oil production system, a linear motor automatic control circuit assembly is disclosed to include a linear motor power supply circuit, a CPU, an insulated gate bipolar transistor driving circuit, a current detection circuit, a temperature sensor, a fluid depth sensor, a function setting and status display circuit, and a circuit assembly power supply circuit for controlling the operation speed of the linear motor subject to the submergence depth of the linear motor in the oil well.

An n-type first base layer is formed on a semiconductor substrate 1 having a first major surface and a second major surface, and a p-type second base layer is formed thereon. Between the first base layer and the second base layer, a carrier stored layer is formed. The carrier stored layer has a high-concentration impurity layer and a low concentration impurity layer, and the high-concentration impurity layer has a thickness of 1.5 μm or more and an impurity concentration therethrough is made to be 1.0×1016 cm−3 or more throughout the layer.

Systems, methods and devices which utilize Spread Spectrum Time Domain Reflectometry (SSTDR) techniques to measure degradation of electronic components are provided. Such measurements may be implemented while the components “live” or otherwise functioning within an overall system. In one embodiment, monitoring a power converter in a high power system is accomplished. In this embodiment, degradation of components within the power converter (e.g. metal-oxide-semiconductor field-effect transistors (MOSFETs), capacitors, insulated-gate bipolar transistors (IGBTs), and the like) may be monitored by processing data from reflections of an SSTDR signal to determine changes in impedance, capacitance, or any other changes that may be characteristic of components degrading. For example, an aging MOSFET may experience an increase of drain to source resistance which adds additional resistance to a current path within a power converter. Such a change is able to be analyzed monitored upon processing the reflected test signals.

This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

The invention relates to a protection circuit driven by insulated gate bipolar transistor (IGBT). It is composed of power supply, IGBT, a signal circuit driven by upper and lower bridges, light coupler, a control circuit with a switch triode, an amplifying circuit for driving signal, a protection circuit for detecting and adjusting the voltages between collector and emitter of IGBT. Said protection circuit includes a short circuit protection circuit, fault latching circuit and fault soft switch off circuit. When the voltage of collector-emitter of IGBT is abnormal, the voltage of insulated gate of IGBT is adjusted to lower than threshold voltage, by the operation of short circuit protection circuit as well as control and amplifying circuit. Thus the IGBT is cut-off and the close latching is realized by that fault latching circuit. It guarantees to close off IGBT before CPU receives the fault signal and closes off driving signal.

A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.

An IGBT includes a first silicon region over a collector region, and a plurality of pillars of first and second conductivity types arranged in an alternating manner over the first silicon region. The IGBT further includes a plurality of well regions each extending over and being in electrical contact with one of the pillars of the first conductivity type, and a plurality of gate electrodes each extending over a portion of a corresponding well region. The physical dimensions of each of the first and second conductivity type pillars and the doping concentration of charge carriers in each of the first and second conductivity type pillars are selected so as to create a charge imbalance between a net charge in each pillar of first conductivity and a net charge in its adjacent pillar of the second conductivity type.

An IGBT is provided which comprises N+ type extended region 9 sectively formed in P+ type collector region 1 to define a built-in diode in cooperation with N+ type extended region 9, an N− type base region 2 and a P− type base region 3 in semiconducting substrate 10. N− type base region 2 comprises a recombination region 21 developed between P type base region 3 and collector electrode 8 to acquire minority carriers accumulated around recombination region 21 in first base region 2 by recombination region 21 for improvement in recovery property of the diode without increasing voltage in the forward direction since recombination region 21 does not reach between and beneath adjoining second base regions 3 in N type base region 2 for current path.

The invention provides a method and a system for calculating the transient junction temperature of an IGBT (Insulated Gate Bipolar Translator) module. The method comprises the steps of: acquiring circuit state information, loss parameter and internal thermistor voltage drop information; calculating power module loss according to the circuit state information and the loss parameter, and calculating substrate temperature according to the internal thermistor voltage drop information of the module; according to the temperature information provided by internal chips and the internal thermistor of the module as reference temperature, in consideration with thermal coupling between the internal chips of the power module at the same time, establishing a simpler IGBT module thermistor network model, and calculating a junction temperature rise according to the power module loss and the thermistor network model; and calculating the transient junction temperature according to the substrate temperature and the junction temperature rise, thus realizing on-line acquisition of the transient working junction temperature of the IGBT. By sufficiently utilizing the existing thermistor resource inside the power module, a junction temperature measurement system based on a power module electro-thermal coupling model is established, so that accurate power device junction temperature information is provided for security operation and health management of a converter system.

The invention relates to a sub-module circuit board used for a dynamic simulation test for simulating a high-capacity multi-level modular converter (MMC). A digital controller on the circuit board is used for controlling a plurality of MMC sub-modules of which parameters are reduced according to an exponential method, the sub-modules are connected in series. Each MMC sub-module comprises a main circuit an insulated gate bipolar transistor (IGBT) and silicon controlled rectifier driving circuit, a capacitance and voltage sampling circuit, a circuit board isolation power supply, a control and coding-decoding chip shared by a plurality of sub-modules, and a fiber channel, wherein the main circuit a capacitor, two IGBTs which are connected vertically in series and connected with the capacitor in parallel, a bypass switch connected with the lower IGBT in parallel, and a silicon controlled rectifier which is used for protecting the IGBTs and the capacitor and connected with the lower IGBT.

The invention provides an IGBT (insulated gate bipolar transistor) conjunction temperature detection device and a method thereof, wherein the method comprises the following steps of: detecting the switch frequency of an IGBT and the current the IGBT in a conduction state; then calculating the conjunction temperature rise of the IGBT according to a preset model; and then adding the conjunction temperature rise of the IGBT and the temperature of an IGBT heat radiator, and taking the sum of the conjunction temperature rise of the IGBT and the temperature of the IGBT heat radiator as the conjunction temperature of the IGBT, and thus the conjunction temperature of the IGBT can be reflected well. Therefore, the conjunction temperature (obtained by the device and the method) of the IGBT is more accurate than the conjunction temperature (estimated indirectly through detecting the pole plate temperature or the temperature of the heat radiator) of the IGBT in the prior art.

A power control system may use power semiconductor devices such as insulated gate bipolar transistors (IGBT's) in a switching unit to provide motor control. The IGBT's may be cooled with a system that is configured and sized to provide proper cooling at steady-state operating conditions of the switching unit. The IGBT's may be placed in thermal communication with a compartment that may contain phase change material (PCM). When and if the switching unit is operated under transient high load conditions, excess heat may be absorbed by melting of the PCM. When steady state operating conditions are restored the PCM may solidify and release its latent heat to a coolant. The PCM may thus act as a thermal buffer for the cooling system and thus may provide that the cooling system may be minimally sized.

This invented driving protection circuit for inverse impadance insulated-gate bipolar transistor is composed of: (1). a controller; (2). a three-section driving circuit, comprising a dynamic charging current source, a dynamic discharging current source a push-pull amplifier circuit series connected with them; (3). a detecting circuit, when the device being of power-on, it cotnrols the rising-rate of the current at the collector; on the other hand, when power-off, it controls the rising-rate of the voltage at the collector; and (4). a RB-IGBT over-current protection circuit for V(Ce) detection, being connected to the collector of said inverse impadance insulated-gate bipolar transistor. It has two V(Ce) detection schemes.

Silicon carbide high voltage semiconductor devices and methods of fabricating such devices are provided. The devices include a voltage blocking substrate. Insulated gate bipolar transistors are provided that have a voltage blocking substrate. Planar and beveled edge termination may be provided.

A non-volatile memory array includes memory cells connected in a common source arrangement and formed in columns of isolated well regions so that Fowler-Nordheim tunneling is used for both write and erase operations of the memory cells. The memory arrays can be formed as NOR arrays or NAND arrays. In one embodiment, the memory array of the present invention is formed as a byte alterable EEPROM with parallel access. In another embodiment, an insulated gate bipolar transistor (IGBT) is coupled to the memory cells to increase the cell read current of the memory array. When the memory array incorporates IGBTs on the bitlines, the cell read current becomes independent of the wordline voltages. Thus, the memory array of the present invention can be operated at low voltages. The use of IGBTs in the memory array of the present invention enables formation of embedded non-volatile memories in low-voltage digital integrated circuits.

The invention discloses a control circuit for cookware material judgment and a method thereof. The method comprises the following steps: when an electromagnetic heating device works, a control unit controls an IGBT (Insulated Gate Bipolar Transistor) so as to enable a heating unit to heat; a signal generating unit outputs pulse signals to an MCU (Micro Controller Unit) of the control unit correspondingly according to the on / off state of the IGBT; the MCU records the input pulse signals and converts the pulse signals into frequency M; the frequency M is compared with preset frequency threshold N, and the type of cookware is determined to be A when the frequency M is higher than the preset frequency threshold N; the type of the cookware is determined to be B when the frequency M is less than or equal to the preset frequency threshold N; and the MCU adjusts related heating parameters according to the determined type of the cookware, so as to enable the electromagnetic heating device to adjust a heating state. The control circuit and the method have the advantages that an electromagnetic oven can be adjusted into a working state corresponding to the material of the cookware, the material of the cookware is judged in good time so as to carry out error check, and the like; and the material of the cookware is accurately updated so as to adjust the heating state and increase the heating efficiency.