1455 results about "Field oxide" patented technology

In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO2 film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.

In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO2 film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.

A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; and forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions, wherein forming the gate lines also includes forming recesses in the semiconductor substrate between the gate lines, the recesses exposing portions of the semiconductor substrate.

A transverse ultra-thin insulated gate bipolar transistor having current density includes: a P substrate, where the P substrate is provided with a buried oxide layer thereon, the buried oxide layer is provided with an N epitaxial layer thereon, the N epitaxial layer is provided with an N well region and P base region therein, the P base region is provided with a first P contact region and an N source region therein, the N well region is provided with an N buffer region therein, the N well region is provided with a field oxide layer thereon, the N buffer region is provided with a P drain region therein, the N epitaxial layer is provided therein with a P base region array including a P annular base region, the P base region array is located between the N well region and the P base region, the P annular base region is provided with a second P contact region and an N annular source region therein, and the second P contact region is located in the N annular source region. The present invention greatly increases current density of a transverse ultra-thin insulated gate bipolar transistor, thus significantly improving the performance of an intelligent power module.

An integrated MEMS device is provided, including, from bottom up, a bonding wafer layer, a bonding layer, an aluminum layer, a CMOS substrate layer defining a large back chamber area (LBCA), a small back chamber area (SBCA) and a sound damping path (SDP), a set of CMOS wells, a field oxide (FOX) layer, a set of CMOS transistor sources / drains, a first polysilicon layer forming CMOS transistor gates, a second polysilicon layer, said CMOS wells, said CMOS transistor sources / drains and said CMOS gates forming CMOS transistors, an oxide layer embedded with a plurality of metal layers interleaved with a plurality of via hole layers, and a gap control layer, an oxide layer, a first Nitride deposition layer, a metal deposition layer, a second Nitride deposition layer, an under bump metal (UBM) layer made of preferably Al / NiV / Cu and a plurality of solder spheres.

A compact MEMS motion sensor device is provided, including a CMOS substrate layer, with plural anchor posts having an isolation oxide layer surrounding a conductive layer. On one side of CMOS substrate layer, the device further includes a field oxide (FOX) layer, a first set and a second set of implant doped silicon areas, a first polysilicon layer, an oxide layer embedded with plural metal layers interleaved with via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. On the other side of CMOS substrate layer, the present invention further includes a backside interconnect isolation oxide layer, a first MEMS bonding layer, a first metal compound layer, a second MEMS bonding layer, a MEMS layer, a first MEMS eutectic bonding layer, a second metal compound layer, a second MEMS eutectic bonding layer, and a MEMS cap layer.

In a method of manufacturing a non-volatile memory or other semiconductor device, a control gate made of conductive material is formed in a more uniform fashion. The method includes forming a silicon layer on a buffer oxide layer on a semiconductor substrate. After forming the buffer oxide layer, a stopping layer is formed. The control gate of conductive material, such as a floating gate in an EEPROM memory device, is provided by patterning the silicon layer, gate oxide layer, and the substrate, and then, a trench is formed in the upper portion of the substrate. Uniformity is achieved by oxidizing the sidewalls of the trench to create bird's beaks at both upper and lower portions of the control gate material. Then, a field oxide layer that fills up the trench is formed. Because bird's beaks are evenly formed at both upper and lower portions of the control gate material during oxidation of the sidewalls of the trench, it is formed in a more uniform fashion since achieves uniformity is attained by preventing the sidewalls of the floating gate, for example, from having positive slopes.

A double-RESURF LDMOS transistor has a gate dielectric structure including a shallow field “bump” oxide region and an optional raised dielectric structure that provides a raised support for the LDMOS transistor's polysilicon gate electrode. Fabrication of the shallow field oxide region is performed through a hard “bump” mask and controlled such that the bump oxide extends a minimal depth into the LDMOS transistor's drift (channel) region. The hard “bump” mask is also utilized to produce an N-type drift (N-drift) implant region and a P-type surface effect (P-surf) implant region, whereby these implants are “self-aligned” to the gate dielectric structure. The N-drift implant is maintained at Vdd by connection to the LDMOS transistor's drain diffusion. An additional Boron implant is utilized to form a P-type buried layer that connects the P-surf implant to the P-body region of the LDMOS transistor, whereby the P-surf implant is maintained at 0V.

Isolation regions for semiconductor substrates include dielectric-filled trenches and field oxide regions. Protective caps of dielectric materials dissimilar from the dielectric materials in the main portions of the trenches and field oxide regions may be used to protect the structures from erosion during later process steps. The top surfaces of the isolation structures are coplanar with the surface of the substrate. Field doping regions may be formed beneath the field oxide regions. To meet the demands of different devices, the isolation structures may have varying widths and depths.

A laterally diffused metal-oxide-semiconductor (LDMOS) device as well as a method of making the same is disclosed. A gate is formed on a semiconductor substrate between a source region and a drain region with one side laterally extending onto a part of a field oxide layer and the opposite side beside the source region. A gate dielectric layer is formed between the gate and the semiconductor substrate, wherein the gate dielectric layer comprises two or more portions having different thicknesses arranged laterally in a way that the thicknesses of the portions gradually increase from one side beside the source doping region to the opposite side bordering the field oxide layer. With such structure, the hot carrier impact is minimized and the gate length can be scaled down to gain Idlin.

A metal-oxide-semiconductor transistor device for high voltage (HV MOS) and a method of manufacturing the same are disclosed. The HV MOS transistor device comprises a field oxide region with an indented lower surface combined with a plurality of field plates to elongate the path for disturbing the lateral electric field, therefore the transistor device has a relatively small size.

A drain-extended metal-oxide-semiconductor transistor (40) with improved robustness in breakdown characteristics is disclosed. Field oxide isolation structures (29c) are disposed between the source region (30) and drain contact regions (32a, 32b, 32c) to break the channel region of the transistor into parallel sections. The gate electrode (35) extends over the multiple channel regions, and the underlying well (26) and thus the drift region (DFT) of the transistor extends along the full channel width. Channel stop doped regions (33) underlie the field oxide isolation structures (29c), and provide conductive paths for carriers during breakdown. Parasitic bipolar conduction, and damage due to that conduction, is therefore avoided.

A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second polysilicon which has been polished back to be flush with a top surface of a dielectric layer covering the tops of the source and drain contacts. The dielectric layer preferably has a nitride cap to act as a polish stop. In some embodiments, nitride covers the entire dielectric layer covering the source and drain contacts as well as the field oxide region defining an active area for said JFET. An embodiment with an epitaxially grown channel region formed on the surface of the substrate is also disclosed.

A CMOS image sensor includes a plurality of pixel regions formed under a front surface of a substrate, and having photodiodes separated from each other by a field oxide, a multi-layered metal interconnection formed over the pixel regions of the front of the substrate, a bump connected to an uppermost metal interconnection of the multi-layered metal interconnection, a plurality of trenches formed in a backside of the substrate, wherein the trenches have different depths for each wavelength of light, and correspond to the respective pixel regions, and a glass covering the backside of the substrate.

A structure for an antifuse cell which comprises: (a) field oxide between the bottom plate of the antifuse element and its access transistor; and (b) an implanted region underlying the antifuse element to provide a conductive path between the source of the access transistor and the antifuse element.

This invention discloses a method for manufacturing a semiconductor power device in a semiconductor substrate comprises an active cell area and a termination area. The method comprises the steps of a) growing and patterning a field oxide layer in the termination area and also in the active cell area on a top surface of the semiconductor substrate b) depositing and patterning a polysilicon layer on the top surface of the semiconductor substrate at a gap distance away from the field oxide layer; c) performing a blank body dopant implant to form body dopant regions in the semiconductor substrate substantially aligned with the gap area followed by diffusing the body dopant regions into body regions in the semiconductor substrate; d) implanting high concentration body-dopant regions encompassed in and having a higher dopant concentration than the body regions e) applying a source mask to implant source regions having a conductivity opposite to the body region with the source regions encompassed in the body regions and surrounded by the high concentration body-dopant regions; and f) etching contact trenches into the source, body contact, and body regions.

A method for making an array of photodiodes with more uniform optical spectral response for the red, green, and blue pixel cells on a CMOS color imager is achieved. After forming a field oxide on a substrate to electrically isolate device areas for CMOS circuits, an array of deep N doped wells is formed for photodiodes for the long wavelength red pixel cells. An array of P doped well regions is formed adjacent to and interlaced with the N doped wells. Shallow diffused N+ regions are formed within the P doped wells for the shorter wavelength green and blue color pixels cells. The shallow diffused photodiodes improve the quantum efficiency (QE), and provide a color imager with improved color fidelity. An insulating layer and appropriate dye materials are deposited and patterned over the photodiodes to provide the array of color pixel cells. The N and P doped wells are also used for the supporting FET CMOS circuits to provide a cost-effective manufacturing process.

Method and apparatus for a semiconductor device including high voltage MOS transistors is described. A substrate is provided with a low voltage and a high voltage region separated one from the other. Isolation regions containing an insulator are formed including at least one formed within one of said wells within the high voltage region. The angle of the transition from the active areas to the isolation regions in the high voltage device region is greater than a predetermined angle, in some embodiments it is greater than 40 degrees from vertical. In some embodiments the isolation regions are formed using shallow trench isolation techniques. In alternative embodiments the isolation regions are formed using field oxide formed by local oxidation of silicon techniques.

A method of self-aligned shallow trench isolation and a method of manufacturing a non-volatile memory using the same are disclosed. An oxide layer, a first conductive layer and a nitride layer are successively formed on a semiconductor substrate. By using a single mask, the nitride layer, the first conductive layer and the oxide layer are etched to form an oxide layer pattern, a first conductive layer pattern and a nitride layer pattern. Subsequently, the upper portion of the substrate adjacent to the first conductive layer pattern is etched to form a trench. A CVD-oxide layer is deposited on the inner surface of the trench to form a trench inner-wall oxide layer, thereby preventing the formation of a positive profile at the sidewalls of the first conductive layer pattern. The trench inner-wall oxide layer is annealed in an N2O or NO atmosphere to form an oxynitride layer at the interface between the substrate and trench inner-wall oxide layer. Finally, a field oxide layer that fills up the trench is formed. Because the trench inner-wall oxide layer is formed by a CVD method to prevent the sidewalls of the first conductive layer pattern from having positive slopes, a conductive residue does not remain during a subsequent gate etching process.

A compact MEMS motion sensor device is provided, including a CMOS substrate layer, with plural anchor posts having an isolation oxide layer surrounding a conductive layer. On one side of the CMOS substrate layer, the device further includes a field oxide (FOX) layer, a first set and a second set of implant doped silicon areas, a first polysilicon layer, an oxide layer embedded with plural metal layers interleaved with via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. On the other side of the CMOS substrate layer, it further includes a backside interconnect isolation oxide layer, a first MEMS bonding layer, a first metal compound layer, a second MEMS bonding layer, a MEMS layer, a first MEMS eutectic bonding layer, a second metal compound layer, a second MEMS eutectic bonding layer, and a MEMS cap layer.

An electrostatic discharge (ESD) protection device includes a semiconductor layer, a source region formed in the layer, a drain region formed in the layer, a channel region in the layer between the source and drain regions, and a gate over the channel region. A plurality of current divider segments are distributed on the drain region and extend between the gate and drain contacts. The segments can be formed of polysilicon or a field oxide.

A method for fabricating a CMOS image sensor including a low voltage buried photodiode and a transfer transistor, includes the steps of: forming a field oxide for defining active area and field area on certain area of an epitaxial layer formed on a substrate, and forming a gate of transfer transistor on the epitaxial layer of the active area; forming the low voltage buried photodiode doping region in alignment with one side of the gate of transfer transistor and field oxide; forming a spacer insulation layer by stacking layers of oxide and nitride over the whole structure; forming a spacer block mask to open areas excluding doping region for the low voltage buried photodiode; and removing the spacer block mask, and forming a floating diffusion region on other side of the transfer transistor. Alternatively, the sacrificial nitride may be allowed to remain on the surface of the photodiode to improve optical properties for short wavelength lights.

A power Schottky rectifier device and method of making the same are disclosed. The Schottky rectifier device includes a LOCOS structure grown on the bottom of the trenches by using nitride spacer on the sidewall of the trenches as a thermal oxidation mask. A polycrystalline silicon layer is then filled the first trenches. Under LOCOS structure, a p doped region is optionally formed to minimize the current leakage when the device undergoes a reverse biased. A Schottky barrier silicide layer formed by sputtering and annealing steps is formed on the upper surfaces of the epi-layer and the polycrystalline silicon layer. A top metal layer served as anode is then formed on the Schottky barrier silicide layer and extended to cover a portion of field oxide region of the termination trench. A metal layer served as a cathode electrode is then formed on the backside surface of the substrate opposite to the top metal layer.

An integrated MEMS microphone is provided, including, a bonding wafer layer, a bonding layer, an aluminum layer, CMOS substrate layer, an N+ implant doped silicon layer, a field oxide (FOX) layer, a plurality of implant doped silicon areas forming CMOS wells, a two-tier polysilicon layer with selective ion implantation forming a diaphragm, a plurality of implant doped silicon areas forming CMOS source / drain, a gate poly layer forming CMOS transistor gates, said CMOS wells, said CMOS transistor sources / drains and said CMOS gates forming CMOS transistors, an oxide layer embedded with an interconnect contact layer, a plurality of metal layers interleaved with a plurality of via hole layers, a Nitride deposition layer, an under bump metal (UBM) layer and a plurality of solder spheres. Diaphragm is sandwiched between a small top chamber and a small back chamber, and substrate layer includes a large back chamber.

Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.

A miniaturized floating gate (FG) MOSFET radiation sensor system is disclosed, The sensor preferably comprises a matched pair of sensor and reference FGMOSFETs wherein the sensor FGMOSFET has a larger area floating gate with an extension over a field oxide layer, for accumulation of charge and increased sensitivity. Elimination of a conventional control gate and injector gate reduces capacitance, and increases sensitivity, and allows for fabrication using standard low cost CMOS technology. A sensor system may be provided with integrated signal processing electronics, for monitoring a change in differential channel current ID, indicative of radiation dose, and an integrated negative bias generator for automatic pre-charging from a low voltage power source. Optionally, the system may be coupled to a wireless transmitter. A compact wireless sensor System on Package solution is presented, suitable for dosimetry for radiotherapy or other biomedical applications.