767 results about "Antifuse" patented technology

A low-cost memory cell array includes multiple, vertically-stacked layers of memory cells. In one form, each memory cell is characterized by a small cross-sectional area and a read current less than 6.3 microamperes. The resulting memory array has a slow access time and is well-suited for digital media storage, where access time requirements are low and the dramatic cost reductions associated with the disclosed memory arrays are particularly attractive. In another form, each memory cell includes an antifuse layer and diode components, wherein at least one diode component is heavily doped (to a dopant concentration greater than 1019 / cm3), and wherein the read current is large (up to 500 mA).

An improved method for fabricating a three dimensional monolithic memory with increased density. The method includes forming conductors preferably comprising tungsten, then filling and planarizing; above the conductors forming semiconductor elements preferably comprising two diode portions and an antifuse, then filling and planarizing; and continuing to form conductors and semiconductor elements in multiple stories of memories. The arrangement of processing steps and the choice of materials decreases aspect ratio of each memory cell, improving the reliability of gap fill and preventing etch undercut.

Combinations, called matrices with memories, of matrix materials with remotely addressable or remotely programmable recording devices that contain at least one data storage unit are provided. The matrix materials are those that are used in as supports in solid phase chemical and biochemical syntheses, immunoassays and hybridization reactions. The matrix materials may additionally include fluophors or other luminescent moieties to produce luminescing matrices with memories. The data storage units are non-volatile antifuse memories or volatile memories, such as EEPROMS, DRAMS or flash memory. By virtue of this combination, molecules and biological particles, such as phage and viral particles and cells, that are in proximity or in physical contact with the matrix combination can be labeled by programming the memory with identifying information and can be identified by retrieving the stored information. Combinations of matrix materials, memories, and linked molecules and biological materials are also provided. The combinations have a multiplicity of applications, including combinatorial chemistry, isolation and purification of target macromolecules, capture and detection of macromolecules for analytical purposes, selective removal of contaminants, enzymatic catalysis, cell sorting, drug delivery, chemical modification and other uses. Methods for electronically tagging molecules, biological particles and matrix support materials, immunoassays, receptor binding assays, scintillation proximity assays, non-radioactive proximity assays, and other methods are also provided.

The present invention relates to an OTP ROM using a CMOS gate oxide antifuse. According to an embodiment of the present invention, in an OTP ROM cell having a first input terminal, a second input terminal and a third input terminal, wherein the OTP ROM stores data by means of a voltage applied to the first to third input terminals, the OTP ROM cell includes a cell access transistor having a gate and drain forming the second input terminal and a source forming the first input terminal, wherein the cell access transistor is activated by a voltage applied to between the gate and source, a high-voltage blocking transistor having a gate, a drain and a source connected to the drain of the cell access transistor, wherein the high-voltage blocking transistor allows the current to flow from the drain to the source by means of a bias voltage applied to the gate, thus blocking the high voltage applied to the third input terminal from being directly applied to the cell access transistor, and an antifuse transistor having a gate forming the third input terminal, and source and drain both of which are connected to each other and are then connected to the drain of the high-voltage blocking transistor, wherein a high voltage is applied to the third input terminal and if the cell access transistor is activated, gate oxide is broken and shorted.