4257 results about "Block layer" patented technology

An organic electroluminescent element comprising a light emission layer and a hole blocking layer adjacent to the light emission layer, wherein, (i) the light emission layer contains a compound having a specified partial structure and having a molecular weight of not more than 1700; and (ii) the hole blocking layer contains a derivative selected from the group consisting of a styryl derivative, a boron derivative and a carboline derivative.

A laser diode, grown on a miscut nonpolar or semipolar substrate, with lower threshold current density and longer stimulated emission wavelength, compared to conventional laser diode structures, wherein the laser diode's (1) n-type layers are grown in a nitrogen carrier gas, (2) quantum well layers and barrier layers are grown at a slower growth rate as compared to other device layers (enabling growth of the p-type layers at higher temperature), (3) high Al content electron blocking layer enables growth of layers above the active region at a higher temperature, and (4) asymmetric AlGaN SPSLS allowed growth of high Al containing p-AlGaN layers. Various other techniques were used to improve the conductivity of the p-type layers and minimize the contact resistance of the contact layer.

A group III nitride semiconductor light emitting device according to the present invention includes an immediate layer formed of Al_xGa_1-x-yIn_yN (0<x<1, 0<y<1, x+y<1) between an active layer and a cladding layer and an electron blocking layer formed of p-type group III nitride semiconductor having a smaller electron affinity than that of the intermediate layer so as to be in contact with the intermediate layer. The semiconductor light emitting layer may be a laser diode or a LED.

A semiconductor memory device includes a semiconductor substrate, a tunnel insulating layer, charge trap layer, and a blocking layer. The tunnel insulating layer is on the semiconductor substrate. The charge trap layer is on the tunnel insulating layer and includes at least one pair of a first nitride layer with a higher trap density of holes than electrons and a second nitride layer with a higher trap density of electrons than holes. The blocking layer is on the charge trap layer opposite to the tunnel insulating layer. The first nitride layer may include silicon rich nitride, which may have a ratio of silicon to nitride of greater than 1 and less than or equal to 2. The second nitride layer may include aluminum nitride which may have a hexagonal crystalline structure.

A device having thin-film transistor (TFT) floating gate memory cell structures is provided. The device includes a substrate, a dielectric layer on the substrate, and one or more source or drain regions being embedded in the dielectric layer. the dielectric layer being associated with a first surface. Each of the one or more source or drain regions includes an N⁺ polysilicon layer on a diffusion barrier layer which is on a first conductive layer. The N⁺ polysilicon layer has a second surface substantially co-planar with the first surface. Additionally, the device includes a P⁻ polysilicon layer overlying the co-planar surface and a floating gate on the P⁻ polysilicon layer. The floating gate is a low-pressure CVD-deposited silicon layer sandwiched by a bottom oxide tunnel layer and an upper oxide block layer. Moreover, the device includes at least one control gate made of a P⁺ polysilicon layer overlying the upper oxide block layer. A method of making the same memory cell structure is provided and can be repeated to integrate the structure three-dimensionally.

Channel doping is an effective method for controlling Vth, but if Vth shifts to the order of -4 to -3 V when forming circuits such as a CMOS circuit formed from both an n-channel TFT and a P-channel TFT on the same substrate, then it is difficult to control the Vth of both TFTs with one channel dope. In order to solve the above problem, the present invention forms a blocking layer on the back channel side, which is a laminate of a silicon oxynitride film (A) manufactured from SiH4, NH3, and N2O, and a silicon oxynitride film (B)manufactured from SiH4and N2O. By making this silicon oxynitride film laminate structure, contamination by alkaline metallic elements from the substrate can be prevented, and influence by stresses, caused by internal stress, imparted to the TFT can be relieved.

A non-volatile memory device includes a channel layer vertically extending from a substrate, a plurality of inter-layer dielectric layers and a plurality of gate electrodes that are alternately stacked along the channel layer, and an air gap interposed between the channel layer and each of the plurality of gate electrodes. The non-volatile memory device may improve erase operation characteristics by suppressing back tunneling of electrons by substituting a charge blocking layer interposed between a gate electrode and a charge storage layer with an air gap, and a method for fabricating the non-volatile memory device.

An implementing mode of the invention provides an improved technology for depositing materials containing tungsten. The technology utilizes an infusion technology and a gaseous phase deposition technology, such as atomic layer deposition (ALD), to provide tungsten-containing materials with obviously improved surface evenness and yield. In one implementing mode, a method for forming tungsten-containing materials on a substrate is provided. The method comprises deposing a substrate, which contains a bottom coating deposited thereon, in a technological chamber; exposing the substrate orderly in a precursor of tungsten and reducing gases so as to deposit a tungsten nucleation layer on the bottom coating, during the ALD technology; and depositing a tungsten block layer on the tungsten nucleation layer. The invention is characterized in that the reducing gases comprise a hydrogen gas/hydride flow ratio of 40:1, 100:1, 500:1, 800: 1, 1000:1 or more, and comprise hydride such as diborane, silicane or silicoethane.

A photoelectric conversion element comprises a photoelectric conversion section that includes: a pair of electrodes; and a photoelectric conversion layer disposed between the pair of electrodes, wherein the photoelectric conversion section further comprises between one of the pair of electrodes and the photoelectric conversion layer a first charge-blocking layer that restrains injection of charges from the one of the electrodes into the photoelectric conversion layer when a voltage is applied to the pair of electrodes, and the first charge-blocking layer comprises a plurality of layers.

Non-volatile memory devices and arrays are described that utilize reverse mode non-volatile memory cells that have band engineered gate-stacks and nano-crystal charge trapping in EEPROM and block erasable memory devices, such as Flash memory devices. Embodiments of the present invention allow a reverse mode gate-insulator stack memory cell that utilizes the control gate for programming and erasure through a band engineered crested tunnel barrier. Charge retention is enhanced by utilization of high work function nano-crystals in a non-conductive trapping layer and a high K dielectric charge blocking layer. The band-gap engineered gate-stack with symmetric or asymmetric crested barrier tunnel layers of the non-volatile memory cells of embodiments of the present invention allow for low voltage tunneling programming and erase with electrons and holes, while maintaining high charge blocking barriers and deep carrier trapping sites for good charge retention.

Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode.

A photoconductive imaging member comprised of a supporting substrate, a hole blocking layer, an optional adhesive layer, a photogenerator layer, and a charge transport layer, and wherein said blocking layer is comprised of a polyhaloalkylstyrene.

A non-volatile semiconductor memory device comprises a substrate including a source region, a drain region and a channel region provided between the source region and the drain region with a gate stack located above the channel region with a metal gate located above the gate stack. The metal gate is comprised of a metal having a specific metal work function relative to a composition of a layer of the gate stack that causes electrons to travel through the entire thickness of the blocking layer via direct tunneling. The gate stack preferably comprises a multiple layer stack selected from a group of multiple layer stacks consisting of: ONO, ONH, OHH, OHO, HHH, or HNH, where O is an oxide material, N is SiN, and H is a high κ material.

An organic photoelectric conversion element comprises: a pair of electrodes; an organic photoelectric conversion layer arranged between the pair of electrodes; and an positive hole blocking layer arranged between one of the pair of electrodes and the organic photoelectric conversion layer, wherein an ionization potential of the positive hole blocking layer is larger than a work function of the adjoining electrode by 1.3 eV or more, and wherein an electron affinity of the positive hole blocking layer is equal to or larger than that of the adjoining organic photoelectric conversion layer. An electron blocking layer may be arranged between the other one of the pair of electrodes and the organic photoelectric conversion layer, wherein its electron affinity is smaller than a work function of the adjoining electrode by 1.3 eV or more, and its ionization potential is equal to or smaller than that of the adjoining organic photoelectric conversion layer.

To increase the detection sensitivity of a touch panel, provide a thin touch panel, provide a foldable touch panel, or provide a lightweight touch panel. A display element and a capacitor forming a touch sensor are provided between a pair of substrates. Preferably, a pair of conductive layers forming the capacitor each have an opening. The opening and the display element are provided to overlap each other. A light-blocking layer is provided between a substrate on the display surface side and the pair of conductive layers forming the capacitor.

A display apparatus is provided that prevents shortening of the life of the luminescent elements and has a superior contrast ratio. The display apparatus is composed by forming a plurality of luminescent elements on a substrate and providing bank sections between each of the luminescent elements. The bank sections are formed from a first bank layer located on the side of the substrate and a second bank layer formed on the first bank layer. A light blocking layer is then provided between the first bank layer and the second bank layer.

A method for fabricating a vertical channel type nonvolatile memory device includes forming alternately a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, forming a trench having a plurality of recesses on a surface of the trench by etching the plurality of interlayer dielectric layers and a plurality of conductive layers, wherein the plurality of recesses are formed at a certain interval on the surface of the trench, forming a charge blocking layer over a plurality of surfaces of the plurality of recesses, forming a charge storage layer over the charge blocking layer for filling a plurality of the remaining recesses with a charge storage material, forming a tunnel dielectric layer to cover the charge storage layer, and forming a vertical channel layer by filling the remaining trench.

A band gap engineered, charge trapping memory cell includes a charge trapping element that is separated from a metal or metal compound gate, such as a platinum gate, by a blocking layer of material having a high dielectric constant, such as aluminum oxide, and separated from the semiconductor body including the channel by an engineered tunneling dielectric. Fast program and erase speeds with memory window as great as 7 V are achieved.

A laminated body is formed by alternately laminating a plurality of dielectric films and electrode films on a silicon substrate. Next, a through hole extending in the lamination direction is formed in the laminated body. Next, a selective nitridation process is performed to selectively form a charge layer made of silicon nitride in a region of an inner surface of the through hole corresponding to the electrode film. Next, a high-pressure oxidation process is performed to form a block layer made of silicon oxide between the charge layer and the electrode film. Next, a tunnel layer made of silicon oxide is formed on an inner side surface of the through hole. Thus, a flash memory can be manufactured in which the charge layer is split for each electrode film.