135 results about "Trap density" patented technology

A semiconductor memory device includes a semiconductor substrate, a tunnel insulating layer, charge trap layer, and a blocking layer. The tunnel insulating layer is on the semiconductor substrate. The charge trap layer is on the tunnel insulating layer and includes at least one pair of a first nitride layer with a higher trap density of holes than electrons and a second nitride layer with a higher trap density of electrons than holes. The blocking layer is on the charge trap layer opposite to the tunnel insulating layer. The first nitride layer may include silicon rich nitride, which may have a ratio of silicon to nitride of greater than 1 and less than or equal to 2. The second nitride layer may include aluminum nitride which may have a hexagonal crystalline structure.

A semiconductor device and a method of manufacturing the device using a (000-1)-faced silicon carbide substrate are provided. A SiC semiconductor device having a high voltage resistancehigh blocking voltage and high channel mobility is manufactured by opting the heat treatment method used following the gate oxidation. The method of manufacturing a semiconductor device includes the steps of forming a gate insulation layer on a semiconductor region formed of silicon carbide having a (000-1) face orientation, forming a gate electrode on the gate insulation layer, forming an electrode on the semiconductor region, cleaning the semiconductor region surface. The gate insulation layer is formed in an atmosphere containing 1% or more H₂O (water) vapor at a temperature of from 800° C. to 1150° C. to reduce the interface trap density of the interface between the gate insulation layer and the semiconductor region.

The invention discloses a measuring device and method for a trap parameter of solid dielectric. The solid dielectric material is charged by using a three-electrode corona discharge system; a material sample to be tested is placed below a single-needle electrode and a metal mesh electrode; the sample is adhered to a metal disc electrode through conductive silicone grease and is charged by the three-electrode system; after charging is ended, an external voltage is removed, and short circuit discharge is performed to remove surface free loads; surface potential of the measured sample is attenuated; and the trap energy level and the trap density parameter of the material can be calculated through a signal conditioning circuit and a data acquisition system. The measuring device comprises a constant temperature box, the three-electrode coronate charging system, a surface potential measuring system, a sample preheating system, a rotary electrode and a temperature and humidity control system. The invention provides an effective analysis means for research in representation of an aging condition of a polymer insulating material and an aging rule of polymer by the trap parameter and research in aspects such as a solid dielectric surface electrification phenomenon and surface flashover performance influence.

An active region or channel for printed, organic or plastic electronics or polymer semiconductors, such as organic field-effect transistors (OFETs), is obtained by using an enhanced inkjet drop-cast printing technique. A two-liquid system is employed to achieve the direct growth of well-oriented organic crystals at the active region of channel. High-performance electrical properties exhibiting high carrier mobility and low threshold voltage are obtained due to the proper orientation of molecules in the grown crystal in a highest mobility direction, due to the absence of grain boundaries, and due to low trap densities. The hydrophobic-hydrophilic interactions between the liquids utilized, which results in the fabrication of low-cost and mass-producible printable electronic devices for applications in flexible displays, electronic signages, photovoltaic panels, membrane keyboards, radio frequency identification tags (RFIDs), electronic sensors, and integrated electronic circuits.

A method for manufacturing a silicon carbide semiconductor device. In one embodiment, the method includes the following steps: a layer of silicon dioxide is formed on a silicon carbide substrate to create a silicon dioxide/silicon carbide interface and then nitrogen is incorporated at the silicon dioxide/silicon carbide interface for reduction in an interface trap density. The silicon carbide substrate, in one embodiment, includes a n-type 4H-silicon carbide.

A semiconductor device including a bilayer charge storing layer and methods of forming the same are provided. Generally, the method includes: (i) forming a first layer of the bilayer charge storing layer; and (ii) forming a second layer formed on a surface of the first layer, the second layer including an oxynitride charge trapping layer. Preferably, the first layer includes a substantially trap free oxynitride layer. More preferably, the oxynitride charge trapping layer includes a significantly higher stoichiometric composition of silicon than that of the first layer. In certain embodiments, the oxynitride charge trapping layer has a concentration of carbon selected to increase the number of traps therein. Other embodiments are also disclosed.

A method for measuring defect parameter of polymer insulation material includes setting a multi-needle electrode in insulated box, sticking test sample of said material grounding metal disc electrode in said box, placing multi-needle electrode above test sample to charge said test sample by utilizing high voltage DC power, moving test sample onto another grounding disc electrode to use short-circuit to discharge said test sample, utilizing capacity electrostatic probe to measure out surface potential of said test sample and obtaining defect energy level and defect density of insulation material through calculation.

Provided is a nonvolatile memory device which includes a tunneling insulating film formed on a semiconductor substrate, a storage node formed on the tunneling insulating film, a blocking insulating film formed on the storage node, and a control gate electrode formed on the blocking insulating film. The storage node includes at least two trapping films having different trap densities, and the blocking insulating film has a dielectric constant greater than that of the silicon oxide film.

A thin film solar cell structure and the fabricating method thereof are disclosed. A passivation layer is embedded into the thin film solar cell structure to be in contact with an absorbing layer. The interface trap density of the absorbing layer is reduced by the surface electric field of the passivation layer. The invention helps improve the power conversion efficiency and protect the absorbing layer.

Methods and systems for determining a charge trap density between a semiconductor material and a dielectric material are disclosed. In one respect, spectroscopic data of the semiconductor material may be determined and used to determine a change in dielectric function. A line shape fit of the change in the dielectric function may be applied using derivative function form. The amplitude of the line shape fit may be determined and used to determine an electric field of a space charge region of the semiconductor material. By applying Poisson's equations, the scalar potential due to the electric field in the space charge region may be determined. Subsequently, using the scalar potential the charge trap density may be determined.

The invention discloses a gate-oxidizing-layer interface-trap density-testing structure and testing method, which relates to the technical field of the quality and reliability testing for MOS (Metal Oxide Semiconductor) devices. The testing structure comprises an n-type MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) and a corresponding p-type gate-oxidizing-layer capacitor or a p-type MOSFET and a corresponding n-type gate-oxidizing-layer capacitor; and the n-type MOSFET and the corresponding p-type gate-oxidizing-layer capacitor or the p-type MOSFET and the corresponding n-type gate-oxidizing-layer capacitor are shared with a grid electrode. The testing for the gate-oxidizing-layer interface-trap density of n-type and p-type MOS devices can be finished by adopting the same testing structure according to the invention, so that the measuring time is shortened, the testing efficiency is improved, and the testing cost is lowered.

A method of manufacturing a semiconductor device based on a SiC substrate (12), comprising the steps of forming (201) an oxide layer (14) on a Si-terminated face of the SiC substrate (12) at an oxidation rate sufficiently high to achieve a near interface trap density below 5×10¹¹ cm⁻²; and annealing (202) the oxidized SiC substrate in a hydrogen-containing environment, in order to passivate deep traps formed in the oxide-forming step, thereby enabling manufacturing of a SiC-based MOSFET (10) having improved inversion layer mobility and reduced threshold voltage. It has been found by the present inventors that the density of DTs increases while the density of NITs decreases when the Si-face of the SiC substrate is subject to rapid oxidation. According to the present invention, the deep traps formed during the rapid oxidation can be passivated by hydrogen annealing, thus leading to a significantly decreased threshold voltage for a semiconductor device formed on the oxide.

A diffusion barrier layer is incorporated between a top semiconductor layer and buried oxide layer. The diffusion barrier layer blocks diffusion of dopants into or out of buried oxide layer. The diffusion barrier layer may comprise a dielectric material such as silicon oxynitride or a high-k gate dielectric material. Alternately, the diffusion barrier layer may comprise a semiconductor material such as SiC. Such materials provide less charge trapping than a silicon nitride layer, which causes a high level of interface trap density and charge in the buried oxide layer. Thus, diffusion of dopants from and into semiconductor devices through the buried oxide layer is suppressed by the diffusion barrier layer without inducing a high interface trap density or charge in the buried oxide layer.

A nonvolatile semiconductor memory device includes a semiconductor substrate having a source region and a drain region, and a gate stack formed on the semiconductor substrate between and in contact with the source and drain regions. The gate stack includes, in sequential order from the substrate: a tunneling film; a first trapping material film doped with a first predetermined impurity, the first trapping material film having a higher dielectric constant than the nitride film (Si₃N₄); a first insulating film having a higher dielectric constant than a nitride film; and a gate electrode. Such a nonvolatile semiconductor memory device can effectively control the trap density according to the doping concentration, thereby increasing the write/erase speed of data at a low operating voltage.

A memory device including a dielectric thin film having a plurality of dielectric layers and a method of manufacturing the same are provided. The memory device includes: a bottom electrode; at least one dielectric thin film disposed on the bottom electrode and having a plurality of dielectric layers with different charge trap densities from each other; and an top electrode disposed on the dielectric thin film. Therefore, a memory device, which can be readily manufactured by a simple process and can be highly integrated using its simple structure, can be provided.