1340results about How to "Lower threshold voltage" patented technology

Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the present invention reduces the power dissipation and improves the timing of an integrated circuit to optimize the design. A thermal analysis is used to determine the temperature dependent power dissipation of a circuit and the temperature distribution of the circuit resulting from dissipating the heat created by the temperature dependent power dissipation. Then, the components of the design are selectively transformed to reduce the power dissipation and to improve timing based on the temperature solution. The transformation may include placement changes and netlist changes, such as the change of transistor threshold voltages for cells or for blocks of the circuit chip.

The present invention relates to erase and program methods of a flash memory device including MLCs for increasing the program speed. In the erase method according to the present invention, MLCs are pre-programmed so that a voltage range in which threshold voltages of MLCs are distributed can be reduced. Therefore, a fail occurrence ratio can be reduced when erasing MLCs, the threshold voltage distribution of MLCs can be improved and an overall program time can be shortened in a subsequent program operation.

The present disclosure discloses a MOSFET and a method for manufacturing the same, wherein the MOSFET comprises: an SOI wafer which comprises a semiconductor substrate, a buried insulating layer, and a semiconductor layer, the buried insulating layer being on the semiconductor substrate, and the semiconductor layer being on the buried insulating layer; a gate stack on the semiconductor layer; a source region and a drain region, which are in the semiconductor layer and on opposite sides of the gate stack; and a channel region, which is in the semiconductor layer and sandwiched by the source region and the drain region, wherein the MOSFET further comprises a back gate, the back gate being located in the semiconductor substrate and having a first doped region in a lower portion of the back gate and a second doped region in an upper portion of the back gate. The MOSFET can adjust the threshold voltage by changing the doping type and doping concentration of the anti-doped region.

Methods and resulting structure of implementing a compensating implant that creates more compensation doping as the gate length is increased are disclosed. In particular, the invention performs an angled compensation implant through a gate opening during the damascene process such that the compensating dopant concentration increases as the gate length increases. In this fashion, the threshold voltage of a longer device is reduced much more than the threshold voltage of a shorter device, thereby reducing the threshold voltage of the longer device to acceptable levels without affecting the threshold voltage of the shorter device. The invention is especially advantageous relative to super-steep retrograde wells.

A method utilizing a common gate electrode material with a single work function for both the pMOS and nMOS transistors where the magnitude of the transistor threshold voltages is modified by semiconductor band engineering and article made thereby.

A memory circuit includes a latch having a first node and a second node to store data such that a logic level of the first node is an inverse of a logic level of the second node, a MIS transistor having a gate node, a first source/drain node, and a second source/drain node, the first source/drain node coupled to the first node of the latch, and a control circuit configured to control the gate node and second source/drain node of the MIS transistor in a first operation such that a lingering change is created in transistor characteristics of the MIS transistor in response to the data stored in the latch, wherein the MIS transistor includes a highly-doped substrate layer, a lightly-doped substrate layer disposed on the highly-doped substrate layer, diffusion regions formed in the lightly-doped substrate layer, a gate electrode, sidewalls, and an insulating film.

We report a method of preparation of highly elastic graphene oxide films, and their transformation into graphene oxide fibers and electrically conductive graphene fibers by spinning. Methods typically include: 1) oxidation of graphite to graphene oxide, 2) preparation of graphene oxide slurry with high solid contents and residues of sulfuric acid impurities. 3) preparation of large area films by bar-coating or dropcasting the graphene oxide dispersion and drying at low temperature. 4) spinning the graphene oxide film into a fiber, and 5) thermal or chemical reduction of the graphene oxide fiber into an electrically conductive graphene fiber. The resulting films and fiber have excellent mechanical properties, improved morphology as compared with current graphene oxide fibers, high electrical conductivity upon thermal reduction, and improved field emission properties.

Methods are disclosed for producing highly doped semiconductor materials. Using the invention, one can achieve doping densities that exceed traditional, established carrier saturation limits without deleterious side effects. Additionally, highly doped semiconductor materials are disclosed, as well as improved electronic and optoelectronic devices/components using said materials. The innovative materials and processes enabled by the invention yield significant performance improvements and/or cost reductions for a wide variety of semiconductor-based microelectronic and optoelectronic devices/systems. Materials are grown in an anion-rich environment, which, in the preferred embodiment, are produced by moderate substrate temperatures during growth in an oxygen-poor environment. The materials exhibit fewer non-radiative recombination centers at higher doping concentrations than prior art materials, and the highly doped state of matter can exhibit a minority carrier lifetime dominated by radiative recombination at higher doping levels and higher majority carrier concentrations than achieved in prior art materials. Important applications enabled by these novel materials include high performance electronic or optoelectronic devices, which can be smaller and faster, yet still capture or emit light efficiently, and high performance electronics, such as transistors, which can be smaller and faster, yet cooler.

The present invention provides an organic thin film transistor and method for fabricating the same. The organic thin film transistor has a substrate and a gate electrode that is positioned on the substrate. A gate insulator has a stacked structure comprising an inorganic gate insulator and an organic gate insulator that are positioned on the gate electrode. An organic semiconductor layer is positioned on the gate insulator to overlap the gate electrode. Accordingly, an organic thin film transistor that has flexibility, decreased leakage current, and a low threshold is formed.

A liquid crystal compound represented by formula (1), a liquid crystal composition comprising the compound, and a liquid crystal display device comprising the composition:

For example, R¹ is alkyl having 1 to 20; ring A¹, ring A², ring A³, ring A⁴, ring A⁵, and ring A⁶ are 1,4-cyclohexylene or 1,4-phenylene; Z¹, Z², Z³, Z⁴, Z⁵, and Z⁶ is a single bond; X¹ is hydrogen or halogen; l, m, n, o, p, and q are 0 or 1, and l+m+n+o+p+q is 3.

A metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT) has a substrate in which an electron supply layer is interposed between an electron channel layer and the surface of the substrate. A pair of main electrodes are formed on the surface of the substrate. A recess is formed in the surface of the substrate between the main electrodes. A gate insulation film is formed on the surface of the substrate, at least between the first and second main electrodes, covering the inside walls and floor of the recess. A gate electrode is formed on the gate insulation film, filling in the recess. The gate insulation film has a crystal density of at least 2.9 g/cm³, which mitigates the reduction in threshold voltage caused by the recess.

An optical device including a polarization control photonic crystal. The optical device includes a vertical cavity surface emitting laser. The optical device further includes a lower mirror formed on a substrate. The optical device also includes an upper mirror. An active region is between the lower mirror and the upper mirror. Photons generated in the active region are reflected between the upper mirror and the lower mirror through the active region. An asymmetrical photonic crystal including cavities is optically coupled in the optical device such that one polarization of light is better reflected by the asymmetrical photonic crystal than a competing polarization of light.