Vertical channel type nonvolatile memory device and method for fabricating the same

Abstract

A method for fabricating, a vertical channel type nonvolatile memory device includes: alternately forming a plurality of sacrificial layers and a plurality of interlayer dielectric layers over a semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form a plurality of first openings for channel each of which exposes the substrate; filling the first openings to form a plurality of channels protruding from the semiconductor substrate; etching the sacrificial layers and the interlayer dielectric layers to form second openings for removal of the sacrificial layers between the channels; exposing sidewalls of the channels by removing the sacrificial layers exposed by the second openings; and forming a tunnel insulation layer, a charge trap layer, a charge blocking layer, and a conductive layer for gate electrode on the exposed sidewalls of the channels.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS[0001]The present application claims priority of Korean Patent Application Nos. 10-2008-0133015 and 10-2009-0031902, filed on Dec. 24, 2008, and Apr. 13, 2009, respectively, the disclosure of each of which is incorporated herein by reference in their entirety.BACKGROUND OF THE INVENTION[0002]The present invention relates to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a vertical channel type nonvolatile memory device and a method for fabricating the same.[0003]Memory devices are classified into volatile memory devices and nonvolatile memory devices according to whether data is retained when power is interrupted. Volatile memory devices lose data when power is interrupted. Examples of volatile memory devices include dynamic random access memory (DRAM) and static random access memory (SRAM). In contrast, nonvolatile memory devices retain stored data even when power is interrupted. Examples of nonvo...

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Benefits of technology

[0043]Other objects and advantages of the present invention can be understood by the following description, and become apparent with reference to the embodiments of the present invention.

Problems solved by technology

Volatile memory devices lose data when power is interrupted.

However, planar nonvolatile memory devices fabricated in a single layer over a silicon substrate have limitations in improving integration density due to fine pattern formation as patterning technologies have reached limitations in some aspects.

First, degradation in the layer quality of the tunnel insulation layer 15 causes degradation in date retention characteristic and reliability.

Therefore, there is a difficulty in forming the channels 16 of single crystal silicon.

Therefore, there is a limitation in increasing the integration density of the nonvolatile memory device.

Thus, an area for formation of the word lines 18 at each page is required and thus there is another limitation in increasing the integration density of the memory device.

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