A method for manufacturing a non-
volatile memory device which can increase the
coupling ratio and can avoid affecting the height of a control gate by forming a trench in a
cell region and forming a floating gate in a concave shape in the trench is disclosed. The method comprises: forming a first trench having a first depth on a
silicon substrate of a
peripheral circuit region, burying the same with a
buried oxide film and planarizing the same; forming a second trench having a second depth on the
silicon substrate of the
cell region; carrying out channel
ion implantation to the
cell region, forming a tunnel
oxide film in the second trench and depositing a floating gate material; forming a floating gate by
etching the floating gate material; forming a source / drain junction in the
cell region; forming wells in the
peripheral circuit and cell regions and depositing a
dielectric film; depositing a gate material while leaving the
dielectric film only in the channel portion of the
cell region; and forming a gate in the
peripheral circuit region and a control gate in the
cell region by
etching the gate material.