219results about How to "Improve circuit performance" patented technology

A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source / drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.

A circuit and method for providing a fully integrated DC-DC converter using on-chip switched capacitors is disclosed. A switched capacitor matrix is coupled as a digitally controlled transfer capacitor. A pair of non-overlapping, fixed frequency clock signals is provided to a switched capacitor circuit including the switched capacitor matrix and a load capacitor coupled to the output terminal. A DC input voltage supply is provided. A hysteretic feedback loop is used to control the voltage at the output as a stepped-down voltage from the input by digitally modulating the transfer capacitor using switches in the switch matrix to couple more, or fewer, transfer capacitors to the output terminal during a clock cycle. A coarse and a fine adjustment circuit are provided to improve the regulation during rapid changes in load power. A method of operating the regulator is disclosed.

The inventive electric contact point of a vacuum valve is made of a sintered alloy containing a heat-resistant metal and a high-conductivity metal. The contact point has at least three slit grooves which extend from the central region to the peripheral region of the contact point, and is soldered to an electrode rod which is connected to the contact point. The contact point includes at least three radially extending vane type contact point members each made of a sintered alloy containing a heat-resistant metal and a high-conductivity metal, and soldered to the electrode rod.

A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

A semiconductor device having an electrically erasable programmable read only memory (EEPROM) comprises a contactless array of EEPROM memory cells disposed in rows and columns and constructed over a silicon-on-insulator wafer. Each EEPROM memory cell comprises a drain region, a source region, a gate region, and a body region. The semiconductor device further comprises a plurality of gate lines each connecting the gate regions of a row of EEPROM memory cells, a plurality of body lines each connecting the body regions of a column of EEPROM memory cells, a plurality of source lines each connecting the source regions of a column of EEPROM memory cells, and a plurality of drain lines each connecting the drain regions of a column of EEPROM memory cells. The source lines and the drain lines are buried lines, and the source regions and the drain regions of a column of EEPROM memory cells are insulated from the source regions and the drain regions of the adjacent columns of EEPROM memory cells.

Monolithic microwave integrated circuit (MMIC) components and micro electromechanical systems (MEMS) components are integrated onto a single substrate at a wafer scale, by first performing MMIC and MEMS fabrication on a front face of a thick substrate wafer, bonding the substrate wafer to a cover wafer, thinning the back face of the substrate wafer and, finally, completing MMIC and MEMS fabrication on the back face of the thinned substrate wafer. The fabrication process is facilitated by use of a guard ring between the wafers to provide additional mechanical support to the substrate wafer and to protect the devices while the MMIC / MEMS fabrication is completed, and by a low temperature bonding process to join the substrate wafer and the cover wafer at multiple device cavity seal rings.

Interconnect layers on a semiconductor device containing logic circuits (microprocessors, Asics of others) or random access memory cells (DRAM's) are formed in a manner to significantly reduce the number of shorts between adjacent conductor / vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of a selectively formed barrier layer on the recessed copper surfaces, is controlled to be essentially co-planar with the surrounding insulator surfaces. Because the barrier layers are recessed, shorting of adjacent conductive lines is prevented.

The invention provides a broadband radiating unit and an antenna array. The broadband radiating unit comprises a support Balun, a radiation arm, a feeding core, a positioning dielectric block, a positioning support snap, a parasitic radiation sheet and an oscillator pad. The radiation arm is above the support Balun, and an oscillator body is formed by the support Balun and the radiation arm. The feeding core is in the cylindrical hole of the support Balun and is coated and positioned by the positioning dielectric block. The oscillator pad is under the oscillator body. The parasitic radiation sheet is fixed above the positioning support snap which is fixed above the radiation arm. In antenna array, a PCB protruding column is arranged under the support Balun of each radiation unit, the PCB protruding column goes through a reflection plate and a PCB and then is welded to a microstrip grounding block, one end of the feeding core is connected to the oscillator body by using the mode of coupling feed, and the other end goes through the reflection plate and the PCB and then is welded to a microstrip line. The radiating unit of the invention has the advantage of simple assembly, few solders, flexible wire running of a back PCB, and higher intermodulation stability.

A device having a resistor and a heater disposed proximate to the resistor and capable of raising the temperature of the resistor. The device further includes a dieletric disposed between the heater and the resistor and a tuner electrically coupled to the resistor. The heater adjusts the resistance of the resistor in response to the tuner.

The present invention relates to a magnetic resonance imaging system and a corresponding method having a transmit phase and a receive phase. Further, the present invention relates to a detuning circuit and a corresponding detuning method for detuning an RF receive coil during the transmit phase in such a magnetic resonance imaging system. In high-field MRI systems the transmit mode operating frequency is higher than normal high breakdown voltage rectifiers can handle when they are used to forward bias a passive detuning circuit PIN diode switch. The proposed circuit uses a current-limiting capacitor (C5) in series with a fast (e.g. schottky) rectifier diode (V2) with a reverse breakdown voltage of e.g. 20 volts and a fast reverse recovery time to generate a DC current. The rectifying circuit is isolated from the PIN diode (V1) with a relatively high-value inductor (L2), which ensures that no harmful transient current spikes can flow from the PIN diode anode to the rectifying circuit. The inductor (L2) still passes and maintains the DC current generated by the rectifying circuit through the PIN diode, thus enabling the robust forward-biasing of the PIN-diode during transmit mode. The use of a fast (and thus low-power) rectifier results in less dissipation on the detuning circuit, and helps in fulfilling the surface temperature limits posed on receiver coils.

A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells.

A design method places power gates or switch cells using unoccupied locations of logic cell rows. Two types of such switch cells, filler switches and sealer switches, may be provided using the unoccupied locations. In one embodiment, virtual ground voltage references to the logic cells are routed to their associated switch cells. Because conventional standard cell design and placement techniques achieve only a placement density or utilization between 70-80% (i.e., unoccupied space constitutes between 20 to 30% of the available space in each row of logic cells), by placing the power gate cells in the unoccupied space, the method does not increase the silicon real estate requirement even though the power gate cells are introduced into the design. Optimization techniques may be applied to achieve proper sizing and distribution of power gate cells, so as to avoid a performance penalty due to the power gate cells. In one embodiment, fine-grained power gating is achieved by selectively providing non-power-gated logic cells among power-gated logic cells.

The present invention is related to a depletion or enhancement mode metal transistor in which the channel regions of a transistor device comprises a thin film metal or metal composite layer formed over an insulating substrate.

A method for amplifying a digital signal representative of data to be transmitted by a line driver with pre-emphasis over an output line is provided. The gain of the line driver is varied between an upper value to coincide with switching of the digital signal and a lower value in absence of the digital signal switching. In particular, the varying includes amplifying the digital signal with a first gain for generating an amplified digital signal, delaying the digital signal with a predetermined delay for generating a delayed digital signal, and amplifying the delayed digital signal with a second gain for generating a delayed and amplified digital signal. An ouput signal corresponding to a difference between the amplified digital signal and the delayed and amplified digital signal is output over the output line.

An envelope-tracking power supply modulator (ETSM) supplies power to a radio frequency power amplifier (RFPA) of a radio frequency (RF) circuit according to a baseband envelope signal. The ETSM includes a linear amplifier, a capacitor, a single inductor multiple output (SIMO) switch-mode converter, and a controller. The linear amplifier receives the baseband envelope signal, and has its output terminal coupled to a power input of the RFPA. One terminal of the capacitor is coupled to a reference voltage, and the other terminal is coupled to a power input of the linear amplifier. The SIMO switch-mode converter includes two output terminals. One of the output terminals is coupled to the capacitor and the power input of the linear amplifier, and the other of the output terminals is coupled to the output terminal of the linear amplifier and the power input of the RFPA. The controller controls the SUMO switch-mode converter.

A hybrid circuit phase shifter assembly of RF MEMS switch modules and passive phase delay shifter circuits uses a low loss, preferably flip-chip, interconnection technology. The hybrid circuit assembly approach separates the fabrication of the MEMS switch modules from the fabrication of the passive phase delay circuits thereby avoiding process incompatibilities and low yields and providing substantial production cost savings. In another aspect of the invention, the integration on a common substrate of a MEMS-based hybrid circuit phase shifter assembly behind each of a plurality of radiating elements provides a compact, low cost electronic scanning antenna array.

A self-correcting etching (SCORE) process for fabricating microstructure is provided. The SCORE process of the present invention is particularly useful for reducing preselected features of a hard mask without degrading the variation of the critical dimension (CD) within each wafer. Alternatively, the CD variation of the hard mask features' produced during printing can be substantially reduced by applying SCORE. Hence, ultra-sub-lithographic features (e.g., nanostructures) can be reliably fabricated. Consequently, the method of the present invention can be used to increase the circuit performance, while improving the manufacturing yield.