522 results about "Gate capacitance" patented technology

A FinFET device and a method of lowering a gate capacitance and extrinsic resistance in a field effect transistor, wherein the method comprises forming an isolation layer comprising a BOX layer over a substrate, configuring source / drain regions above the isolation layer, forming a fin structure over the isolation layer, configuring a first gate electrode adjacent to the fin structure, disposing a gate insulator between the first gate electrode and the fin structure, positioning a second gate electrode transverse to the first gate electrode, and depositing a third gate electrode on the fin structure, the first gate electrode, and the second gate electrode, wherein the isolation layer is formed beneath the insulator, the first gate electrode, and the fin structure. The method further comprises sandwiching the second gate electrode with a dielectric material. The fin structure is formed by depositing an oxide layer over a silicon layer.

A resonate gate drive circuit for driving at least one power switching devices recovers energy loss for charging and discharging the input capacitance of the power switching devices. The gate drive circuit charging and discharging the gate capacitor with a high level current, so the switching loss of the power switching devices can also be reduced. The gate drive circuit can clamp and keep the voltage across the gate capacitor to a certain level while the power switching devices turn on, and it can also clamp and keep the voltage across the gate capacitor to almost zero while the power switching devices turn off. The gate drive circuit comprises four small semiconductor bidirectional conducting switching devices connected in full-bridge configuration. An inductor is connected to the two junctions of the full-bridge configuration to help switching the current direction. A capacitor in series with the inductor is necessary for some applications. A bootstrap circuit, which is widely used in conventional gate drive circuitry, is also necessary for this resonant gate drive circuit when it is adopted for high-side and low-side applications.

A DC symmetrical FET switch includes second and third switches connecting the well of the symmetrical FET switch to the drains and the source when the symmetrical FET switch is on. When the three FET's are on, the well, source and drain of the symmetric FET switch all exhibit the same input signal, wherein the drains and source to well capacitances are substantially prevented from draining off any of the input signal, thereby increasing the bandwidth and decreasing the insertion loss of the switch. The second and third switches are also FET switches. An enable signal is connected to the gates of all three FET's turning them on and off together. When the enable is false the FET switches are turned off and their wells are driven to a potential a proper potential. When the FET's are n-type the potential is low and when the FET's are p-types the potential is high. A resistor is provided in the gate drive of the first FET switch that further increases bandwidth and decreases insertion loss of the switch by moving the break frequency of the drain and source to gate capacitances.

A method and apparatus for controlling the feed rate of a rectified AC pulses via a gated rectifier in a low DC voltage and current power supply is disclosed. The gated rectifier outputs gated AC pulses to an input capacitor via a current control diode and / or a zener diode and / or a resistor for charging the input capacitor to a voltage level and a charge capacity commensurate with the low voltage regulator and the low DC current drain. A gate capacitor for accumulating incremental charges of rectified AC pulses fed via a divider network is pre-configured to trigger the gated rectifier, timed by discharging the aggregated charge of a predetermined number of charges to the gate. The input capacitor charged by the gated AC pulses at a rate of one per said determined number to the input capacitor feeds the voltage regulator for powering a low DC current consuming device.

There is provided an EL light-emitting device with less uneven brightness. When a drain current of a plurality of current controlling TFTs is Id, a mobility is μ, a gate capacitance per unit area is Co, a maximum gate voltage is Vgs(max), a channel width is W, a channel length is L, an average value of a threshold voltage is Vth, a deviation from the average value of the threshold voltage is ΔVth, and a difference in emission brightness of a plurality of EL elements is within a range of ±n %, a semiconductor display device is characterized in that A=2⁢Idμ*C0A(Vgs(max)-Vth)2≦WL≦(1+n100-1)2*AΔ⁢ ⁢Vth2Δ⁢ ⁢Vth≦(1+n100-1)*A*L / W

Disclosed is a semiconductor apparatus having an IGBT, which includes a switch SWon 1 for supplying a gate current during an operation for turning on the gate of the IGBT, a switch SWoff 1 for discharging a gate capacitance during an operation for turning off the gate, a switch SWon 2 for increasing the gate current, a timer 14 for turning on the switch SWon 2 in conjunction with the turn-on of the switch SWon 1 and then maintaining the turn-on of the switch SWon 2 only for a first predetermined time, a switch SWoff 2 for increasing the discharge current during the gate turn-off operation, and a timer 15 for turning on the switch SWoff 2 in conjunction with the turn-on of the switch SWoff 1 and then maintaining the turn-on of the switch SWoff 2 only for a second predetermined time.