1266results about How to "Reduce conduction loss" patented technology

An LC parallel resonance circuit is connected in series with the power supply side of the antenna conductor portion. The antenna conductor portion is configured so as to resonate at a frequency slightly lower than the center frequency in the higher frequency band of two frequency bands for transmitting and receiving radio waves. The LC parallel resonance circuit is configured so as to resonate substantially at the center frequency in the lower frequency band for transmitting and receiving a radio wave and be capable of providing to the antenna conductor portion a capacitance for causing the antenna conductor portion to resonate at the center frequency in the higher frequency band. Thus, a circuit for changing the upper and lower frequency bands is not needed. Such a change-over circuit, which is complicated, causes problems in that the conduction loss increases, and the antenna sensitivity deteriorates. Without need of the change-over circuit, the conduction loss can be reduced, the antenna sensitivity can be enhanced and costs can be reduced.

A single-stage input-current-shaping (S<2>ICS) flyback converter achieves substantially reduced conduction losses in the primary side of the S<2>ICS flyback converter by connecting a bypass diode between the positive terminal of a full-bridge rectifier and the positive terminal of an energy-storage capacitor. An effective current interleaving between an energy-storage inductor and the bypass diode is thus obtained in the S<2>ICS flyback converter around the peak of the rectified line voltage, resulting in a significantly reduced input-current ripple and reduced current stress on the switch. Further, by rearranging the rectifiers in the ICS part of the S<2>ICS flyback converter in such a way that the energy-storage capacitor and the ICS inductor are connected to the ac line voltage through only two rectifiers, one diode forward-voltage drop is eliminated, which results in a substantially reduced conduction loss in the primary-side rectifiers.

A small-sized low-loss dielectric resonator, dielectric filter, and dielectric duplexer, and a communication device using such an element. Through-holes are formed in a dielectric block. The inner surface of each through-hole is covered with a thin-film multilayer electrode consisting of an outermost conductive layer and a multilayer region including thin-film conductive layers and thin-film dielectric layers. An outer conductor having a similar thin-film multilayer electrode structure is formed on the outer surface of the dielectric block. An outer conductor in the form of a single-layer electrode is formed on a short-circuited end face of the dielectric block thereby connecting together the thin-film conductive layers of the inner and outer conductors.

A converter has a transformer with primary and secondary windings each having n coils in a series-series arrangement connected to primary and secondary sides. The primary side has n primary legs each having a top switch and a bottom switch and connected to the primary winding therebetween. The secondary side has n secondary legs, each secondary leg has a synchronous rectifier switch and an output filter inductor connected to the secondary winding therebetween. A complimentary control for the primary side comprising a gate driver transformer with primary winding in series with a DC blocking capacitor connected to a drain and a source of the top switch of each primary leg, and a gate drive transformer, for each primary leg, with secondary winding containing a leakage inductor and in series with a DC blocking capacitor and a damping resistor connected to gate and source of the secondary side synchronous rectifier.

The invention relates to a high power factor DCM Boost PFC converter comprising a main power circuit and a control circuit. The main power circuit comprises an input voltage source vin, an EMI filter, a diode rectification circuit RB, a Boost inductor Lb, a switch tube Qb, a diode Db, an output capacitor Co and a load RLd. The high power factor DCM Boost PFC converter is characterized in that the control circuit adopts an output signal which adopts duty ratio as changing rule to drive the switch tube Qb. Adopting the varying duty ratio control, the high power factor DCM Boost PFC converter can improve the PF value to about 1 in the AC input voltage range of 90-265 V, increase the inductance capacity, obviously decrease the inductive current ripple, obviously reduce the effective value of the inductive current and correspondingly reduce the effective value of the current of the switch tube, has high input power factor and small output voltage ripple and contains less input current harmonic waves. The conduction loss of the high power factor DCM Boost PFC converter is reduced, and the efficiency is improved.

The invention relates to a junction termination structure of a transverse high-pressure power semiconductor device, belonging to the technical field of semiconductor power devices. An N-type drift region at a curvature termination of the transverse high-pressure power semiconductor device is shortened in length to ensure that the N-type drift region is spaced with a P-well region by a certain displace, wherein the spaced part is replaced by a P-type substrate, which is equivalent that additional electric charges of the P-type substrate are introduced so that the peak value of an electric field at a pn junction formed the original P-well region and the N-type drift region is reduced, meanwhile, a new peak value of the electric field is introduced at a pn junction formed by the P-type substrate and the N-type drift region, the radius of curvature of the curvature terminal is increased, the excessive concentration of a power line is avoided, and the puncture voltage of the device is increased, wherein the surface of the N-type drift region also can be combined with a surface RESURF structure or an ultra-junction structure. The junction termination structure has the advantages of being capable of decreasing the width of the curvature terminal of the device, saving the layout area of the device and being compatible with a CMOS (Complementary Metal-Oxide-semiconductor Transistor) process, and can be used for manufacturing the transverse high-pressure power device with the advantages of excellent performance, high voltage, high speed and low conduction loss.

A power supply includes a non-isolated DC-DC converter for use in a power source system having a high side switch and a low side switch, in which HEMT or HFET or gallium nitride device with low capacity and low on-resistance is used for the high side switch and a vertical power MOSFET of silicon device with low on-resistance is used for the low side switch.

A voltage source converter having a plurality of cell modules connected in series, each cell module including a converter unit having an ac-side and a dc-side, and the voltage source converter includes a control unit adapted to control the converter units, where at least one of the cell modules includes a second redundant converter unit having an ac-side which is connected in parallel with the ac-side of the first converter unit and the control unit is configured to substantially synchronously control the first and the second converter units.

A power FET (100) comprising a leadframe including a pad (110), a first lead (111), and a second lead (112); a first metal clip (150) including a plate (150a), an extension (150b) and a ridge (150c), the plate and extension spaced from the leadframe pad and the ridge connected to the pad; a vertically assembled stack of FET chips in the space between the plate and the pad, the stack including a first n-channel FET chip (120) having the drain terminal on one surface and the source and gate terminals on the opposite surface, the drain terminal attached to the pad, the source terminal attached to a second clip (140) tied to the first lead; and a second n-channel FET chip (130) having the source terminal on one surface and the drain and gate terminals on the opposite surface, the source terminal attached to the second clip, its drain terminal attached to the first clip; wherein the drain-source on-resistance of the FET stack is smaller than the on-resistance of the first FET chip and of the second FET chip.

A heat sink and a heat sink assembly that includes the heat sink and a source of flowing air, such as a fan. The heat sink includes a base from which a first plurality of convective surfaces extends. At least one heat pipe is in thermal contact with the base and extends therefrom. The heat pipe includes an evaporator portion in thermal contact with the base and a condenser portion. A second plurality of convective surfaces is in thermal communication with the condenser portion of the heat pipe.

The invention discloses a power factor correction control circuit for reducing EMI (electro magnetic interference), which comprises an inductive current threshold value, wherein when an inductive current is less than the inductive current threshold value, a peak value of the inductive current is controlled to be changed along with an input voltage; and when the inductive current reaches the inductive current threshold value, the inductive current is limited to be the inductive current threshold value. In such a way, the maximum peak of the inductive current is reduced, so that an inductive ripple current is reduced; the power factor is ensured, and the EMI of the circuit is reduced simultaneously, so that circuit filtering can be carried out simply and easily; and the power factor correction control circuit is extremely suitable for occasions with middle or low power. In addition, the peak current stress of the circuit is low, so that a switch tube and other components have small loss, and the utilization ratio of a power supply is further improved. The power factor correction control circuit for reducing the EMI disclosed by the invention meets the requirements of high-power factor and IEC61000-3-2 on the harmonic of the power supply, and has low cost and a small size.

The invention discloses a lithium battery pack SOC (state of charge) equalization system and a lithium battery pack SOC equalization method. The equalization problems of lithium battery packs are divided into two levels, including intra-group equalization and intergroup equalization. Lithium batteries are divided into a plurality of groups, every lithium battery group is in parallel connection with a bidirectional DC-DC converter, the output ends of the bidirectional DC-DC converters are in series connection to serve as the output ends of a direct-current bus and a power generation system, and loads are in parallel connection. The batteries in every group are connected through bilateral switches and are in parallel connection with by-pass switches so as to be connected dynamically. Intergroup equalization is achieved by distributing output voltage of every group according to average SOC thereof; intra-group equalization can be achieved by controlling dynamic connection of every single battery in every group. The lithium battery pack SOC equalization system and the lithium battery pack SOC equalization method have the advantages that lithium battery pack SOC is equalized without an extra equalization circuit, so that energy transfer among the batteries is avoided, lithium battery pack equalization is achieved automatically in a charge-discharge process, the equalization speed is greatly increased and the equalization efficiency is greatly improved.

In accordance with the present invention, a switching converter includes two transistors Q1 and Q2 parallel-connected between two terminals. Transistor Q1 is optimized to reduce the dynamic loss and transistor Q2 is optimized to reduce the conduction loss. Q1 and Q2 are configured and operated such that the dynamic loss of the converter is dictated substantially by Q1 and the conduction loss of the converter is dictated substantially by Q2. Thus, the tradeoff between these two types of losses present in conventional techniques is eliminated, allowing the dynamic and conduction losses to be independently reduced. Further, the particular configuration and manner of operation of Q1 and Q2 enable reduction of the gate capacitance switching loss when operating under low load current conditions.