3760 results about "Thinning" patented technology

A three dimensional device stack structure comprises two or more active device and interconnect layers further connected together using through substrate vias. Methods of forming the three dimensional device stack structure comprise alignment, bonding by lamination, thinning and post thinning processing. The via features enable the retention of alignment through the lamination process and any subsequent process steps thus achieving a mechanically more robust stack structure compared to the prior art.

A surface mount LED package having a tight footprint and small vertical image size is fabricated by a method comprising: forming light emitting diode chips each having a substrate and a plurality of layers configured to emit electroluminescence responsive to electrical energizing; forming electrical vias in a sub mount, the electrical vias passing from a front side of the sub-mount to a back-side of the sub-mount; flip chip bonding the light emitting diode chips on the front-side of the sub mount such that each light emitting diode chip electrically contacts selected electrical vias; thinning or removing the substrates of the flip-chip bonded light emitting diode chips; and after the thinning, disposing a phosphor over the flip chip bonded light emitting diode chips.

A planarization composition is set forth for chemical mechanical planarization of dielectric layers for semiconductor manufacture. The composition comprises spherical silica particles having an average diameter of from 30 nm to about 400 nm, and a narrow range of particle sizes, wherein about 90% of the particles is within 20% of the average particle diameter. The composition includes a liquid carrier comprising up to about 9% alcohol and an amine hydroxide in the amount of about 0.2 to about 9% by weight. The pH of the composition is in the range of about 9 to about 11.5, and the remainder of the solution is water. The composition has low amounts of metal ions, and the composition is used for thinning, polishing and planarizing interlayer dielectric thin films, shallow trench isolation structures, and isolation of gate structures. The invention also comprises methods for using the planarization composition in the manufacture of semiconductor devices.

A die thinning method includes providing a wafer (10) and depositing a substrate bonding material on the wafer. The die thinning method places a plurality of die (12) on the wafer (10), cures the substrate bonding material to secure the individual ICs to the base wafer (10), and covers the substrate (10) and the die (12) with a mask material. The substrate bonding material is BCB. The mask material is a photoresist (14). The method further back grinds the wafer to remove the wafer and to reduce the original die thickness from 26 mils to 5 mils. A UV transfer tape (22) is applied to the die (12) on a film frame (20). The mask material and back grinding tape (18) are then removed. The plurality of die (12), UV transfer tape (22), and film frame (20) are placed face down in a UV cure station. The UV transfer tape (22) is UV irradiated and the plurality of die (12) are removed from the UV transfer tape (22).

A process comprises reducing the thickness of a substrate carrying a plurality of devices, with at least certain of the devices having a micro-machined mesh. A carrier wafer is attached to the back side of the substrate and the fabrication of the devices is completed from the top side of the substrate. Thereafter the plurality of devices is singulated. Various alternative embodiments are disclosed which demonstrate that the thinning of the wafer may occur at different times during the process of fabricating the MEMS devices such as before the mesh is formed or after the mesh is formed. Additionally, the use of carrier wafers to support the thinned wafer enables process steps to be carried out on the side opposite from the side having the carrier wafer. The various alternative embodiments demonstrate that the side carrying the carrier wafer can be varied throughout the process.

After completion of annealing for bonding of the base wafer 1 and bond wafer 2, the bond wafer 2 is thinned to a first thickness suitable for ion implantation, and boron is ion-implanted to thereby form a high-boron-concentration layer 10. A second thinning step based on selective etching is then carried out while using the high-boron-concentration layer 10 as an etch stop layer. This is successful in providing a method of fabricating an SOI wafer which is suppressed both in intra-wafer uniformity of the firm thickness and in inter-wafer uniformity of the film thickness even when a required level for the thickness of the SOI layer is extremely small.

The invention provides an integral forming method of a large size thin-walled titanium alloy cylindrical part without a welding line. The integral forming method comprises the following steps of: (1) tube blank preparation by stamping; (2) high-temperature vacuum heat treatment; (3) heating power spinning thinning; (4) unheating power spinning diameter expanding; (5) repetitive and alternate conduction of steps (3) and (4) for 2-3 times; (6) high-temperature vacuum heat treatment; (7) finish turning treatment; and (8) stabilizing treatment. The integral forming method prepares the large size thin-walled titanium alloy cylindrical part without the welding line (wall thickness is 1-7mm) which has high precision and high performance by utilizing titanium alloy plates and adopting a composite technique combining a stamping method, a spinning method and a stabilizing treatment method, and solves the problems of low material utilization ratio, having longitudinal welding lines, low precision of tube performance and the like in the forging and roll bending welding forming of the large size titanium alloy thin-walled tubes.

A method of etching a deep, high aspect ratio opening in a silicon substrate includes etching the substrate with a first plasma formed using a first gaseous mixture including a bromine containing gas, an oxygen containing gas and a first fluorine containing gas. The etching process with the first gaseous mixture produces a sidewall passivating deposit, which builds up near the opening entrance. To reduce this buildup, and to increase the average etching rate, the sidewall passivating deposit is periodically thinned by forming a second plasma using a mixture containing silane and a second fluorine containing gas. The substrate remains in the same plasma reactor chamber during the entire process and the plasma is continuously maintained during the thinning step. Holes of a depth greater than 40 times the width may be produced using repeated cycles of etching and thinning.

Methods for the conditioning of bioprosthetic material employ bovine pericardial membrane. A laser directed at the fibrous surface of the membrane and moved relative thereto reduces the thickness of the membrane to a specific uniform thickness and smoothes the surface. The wavelength, power and pulse rate of the laser are selected which will smooth the fibrous surface as well as ablate the surface to the appropriate thickness. Alternatively, a dermatome is used to remove a layer of material from the fibrous surface of the membrane. Thinning may also employ compression. Stepwise compression with cross-linking to stabilize the membrane is used to avoid damaging the membrane through inelastic compression. Rather, the membrane is bound in the elastic compressed state through addition cross-linking. The foregoing several thinning techniques may be employed together to achieve strong thin membranes. The finally thinned membrane may then be treated by capping of calcification nucleation sites and borohydride reduction. The leaflets may be formed to have more than one region of uniform thickness, such as a thicker peripheral sewing region.

The invention discloses an image processing method for automatic pointer-type instrument reading recognition. The method comprises the following steps: (1) Hough circle detection is carried out on the image, a weighted average method is used for positioning the circle center and the radius of a dial, and a dial region square image is extracted; (2) the image is pre-treated, and a binary thinning image of the instrument pointer is extracted; (3) a central projection method is used for determining a pointer angle; (4) a zero graduation line and full graduation line position templates are extracted, and a range starting point and ending point positions are calibrated; (5) by using template matching, zero graduation line and full graduation line angles are obtained; and (6) according to the pointer angle, the zero graduation line angle and the full graduation line angle, the pointer reading is obtained through calculation. Thus, the problem that the instrument dial position on the acquired image is not fixed as the relative position between a camera and the pointer-type instrument is not fixed can be solved, subjective errors as the reading of the instrument is read manually can be eliminated, the efficiency and the precision can be improved, safety of people is ensured, the application range is wide, and robustness is strong.

A method and an apparatus for an application thinning mechanism are described. The thinning mechanism can select a subset of components from a universal application to assemble an application variant to be distributed and installed to a specific type of devices. The universal application may include every component, such as asset, resource or executable, built/developed for targeted device attributes to install one common application to multiple devices. For example, the thinning mechanism can use a trait vector associated with a type of devices to iterate through the components and identify assets to be included or packaged into in each target device specific application or application variant.

A thinning or weeding apparatus includes an image processing apparatus. The image processing apparatus includes an automated visual detection system which includes a visual sensor system and an image processing system capable of receiving an image from the visual sensor system. The image processing apparatus then processes the image in the image processing system to determine where plants are located and to determine which plants will be thinned or weeded and which will not.

Sample preparation apparatus and method includes a wafer stage platform with an optical microscope and integrated pattern recognition to automatically address specific locations on the wafer sample of interest. A laser attaches to the optical microscope to mill a set pattern around the area of interest. A precision micro-manipulator engages the sample support structure, extracts the structure, and places the structure in a TEM holder or holder tip. The holder or holder tip can then be placed inside a FIB for final thinning, followed by direct transfer into the TEM.

A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.

The present invention provides SOI CMOS technology whereby a polysilicon back-gate is used to control the threshold voltage of the front-gate device, and the nMOS and pMOS back-gates are switched independently of each other and the front gates. Specifically, the present invention provides a method of fabricating a back-gated fully depleted CMOS device in which the device's back-gate is self-aligned to the device's front-gate as well as the source/drain extension. Such a structure minimizes the capacitance, while enhancing the device and circuit performance. The back-gated fully depleted CMOS device of the present invention is fabricated using existing SIMOX (separation by ion implantation of oxygen) or bonded SOI wafers, wafer bonding and thinning, polySi etching, low-pressure chemical vapor deposition and chemical-mechanical polishing.

A method for precise thinning to form a recess to a precise depth in a crystalline silicon layer, which can be used to form various devices, such as MOSFET devices, includes the following steps. Form a patterning mask with a window therethrough over the top surface of the silicon layer. Form an amorphized region in the top surface of the silicon layer below the window. Selectively etch away the amorphized region of the silicon layer to form a recess in the surface of the silicon layer, and remove the patterning mask. In the case of an MOSFET device form a hard mask below the patterning mask with the window extending therethrough. Then create sidewall spacers in the window through the hard mask and form a gate electrode stack in the window. Then remove the hard mask and form the source/drain extensions, halos and regions plus silicide and complete the MOSFET device.