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357results about How to "Shorten the switching time" patented technology

N-channel LDMOS with buried p-type region to prevent parasitic bipolar effects

InactiveUS6958515B2Reduces base resistance and hence base-emitter voltage dropEfficient collectionSemiconductor/solid-state device detailsSolid-state devicesSafe operating areaBody region
An improved n-channel integrated lateral DMOS (10) in which a buried body region (30), beneath and self-aligned to the source (18) and normal body diffusions, provides a low impedance path for holes emitted at the drain region (16). This greatly reduces secondary electron generation, and accordingly reduces the gain of the parasitic PNP bipolar device. The reduced regeneration in turn raises the critical field value, and hence the safe operating area.
Owner:TEXAS INSTR INC

Method and apparatus for partial duplex protection switching by using single splitter in PON

A method and apparatus for duplex protection switching by using a single splitter in a passive optical network (PON) are provided. The apparatus for duplex protection switching in a PON, in which a single optical line termination (OLT) and many optical network terminations (ONTs) are connected together in a multiple-access manner, includes: a 2:2 splitter connected to two PON line terminations (LTs) in the OLT; and two N:1 splitters which are connected to the 2:2 splitter, and each of which is connected to two PON LTs in the ONT. According to the method and apparatus, an economical effect can be provided in which two links, an operational link and a protection link, in the PON can provide a partial duplex function at a lower cost. Also, a protection switching time can be reduced by simplifying a restoration process so that when an error is detected, an operational state is returned by protection switching.
Owner:ELECTRONICS & TELECOMM RES INST

DC-DC converter

A DC-DC converter includes a switch, a rectifier, a smoothing circuit, and a control circuit. The control circuit includes an output detection circuit for outputting an error signal, a current detection circuit for outputting a current detection signal in a period in which at least the switch is OFF, a first circuit for outputting a first signal for setting a timing of turning ON of the switch according to a comparison result between the error signal and the current detection signal, and a second circuit for outputting a second signal for setting an ON time of the switch, according to a reduction in output power from the smoothing circuit, so that the ON time of the switch is reduced, and generates the control signal, based on the first and second signals.
Owner:PANASONIC CORP
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