7365results about How to "Reduce contact resistance" patented technology

A laser diode, grown on a miscut nonpolar or semipolar substrate, with lower threshold current density and longer stimulated emission wavelength, compared to conventional laser diode structures, wherein the laser diode's (1) n-type layers are grown in a nitrogen carrier gas, (2) quantum well layers and barrier layers are grown at a slower growth rate as compared to other device layers (enabling growth of the p-type layers at higher temperature), (3) high Al content electron blocking layer enables growth of layers above the active region at a higher temperature, and (4) asymmetric AlGaN SPSLS allowed growth of high Al containing p-AlGaN layers. Various other techniques were used to improve the conductivity of the p-type layers and minimize the contact resistance of the contact layer.

To provide a semiconductor device including a thin film transistor having excellent electric characteristics and high reliability and a manufacturing method of the semiconductor device with high mass productivity. The summary is that an inverted-staggered (bottom-gate) thin film transistor is included in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, a channel protective layer is provided in a region that overlaps a channel formation region of the semiconductor layer, and a buffer layer is provided between the semiconductor layer and source and drain electrodes. An ohmic contact is formed by intentionally providing the buffer layer having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrodes.

Provided is a smart garment for measuring a physiological signal which can improve comfort and convenience of wear and correctly measure a physiological signal. The smart garment for measuring physiological signals includes an electrode which is made of an electro-conductive fabric and detects a physiological signal, a physiological signal transmission line through which the detected physiological signal is transmitted, a physiological signal measuring unit which is connected to the transmission line, receives the physiological signal, and measures information regarding body conditions related to the physiological signal, and a pocket where the physiological signal measuring unit in inserted.

Provided is a vertical LED including an n-electrode; an n-type GaN layer formed under the n-electrode, the n-type GaN layer having a surface coming in contact with the n-electrode, the surface having a Ga+N layer containing a larger amount of Ga than that of N; an active layer formed under the n-type GaN layer; a p-type GaN layer formed under the active layer; a p-electrode formed under the p-type GaN layer; and a structure support layer formed under the p-electrode.

A new transparent conducting oxide (TCO), which can be expressed as AlxGa3−x−yIn5+ySn2−zO16−2z; 0≦x<1, 0<y<3, 0≦z<2, has been used to improve the brightness and current spreading in GaN base LED process. The optical properties of this system are superior to regular Ni / Au transparent conducting layer in blue-green region, and the new Al2O3—Ga2O3—In2O3—SnO2 system is able to increase the brightness at 1.5˜2.5 time to compare to regular process. Furthermore, the new transparent conducting oxide thin film has the highest conductivity, which is better than the Ni / Au transparent conducting thin film.

To offer a semiconductor device including a thin film transistor having excellent characteristics and high reliability and a method for manufacturing the semiconductor device without variation. The summary is to include an inverted-staggered (bottom-gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used for a semiconductor layer and a buffer layer is provided between the semiconductor layer and source and drain electrode layers. An ohmic contact is formed by intentionally providing a buffer layer containing In, Ga, and Zn and having a higher carrier concentration than the semiconductor layer between the semiconductor layer and the source and drain electrode layers.

A method of forming a MOS transistor. According to the method of the present invention, a pair of source / drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source / drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source / drain extensions.

A FinFET transistor on SOI device and method of fabrication is provided. At least two FinFET fins each having an upper poly-silicate glass portion and a lower silicon portion are formed using spacer patterning technology. Each fin is formed on a sacrificial SiN mask layer having a sacrificial support structure. The SiN mask is removed and then a breakthrough etch is applied to remove an underlying pad oxide layer. A PSG layer defining a width of each of the fins on a sidewall of each of the support structures is deposited on each of the support structures. At least two fins each having a narrow fin pitch of about 0.25 μm. are formed. The fins provide a seed layer for at least two selective epitaxially raised source and drain regions, wherein each raised source-drain associated with each fin are interconnected thus forming a source pad and a drain pad.

In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

Methods and systems for selectively depositing a p-type doped silicon germanium layer and structures and devices including a p-type doped silicon germanium layer are disclosed. An exemplary method includes providing a substrate, comprising a surface comprising a first area comprising a first material and a second area comprising a second material, within a reaction chamber; depositing a p-type doped silicon germanium layer overlying the surface, the p-type doped silicon germanium layer comprising gallium; and depositing a cap layer overlying the p-type doped silicon germanium layer. The method can further include an etch step to remove the cap layer and the p-type doped silicon germanium layer overlying the second material.

A method and apparatus for fabricating a solar cell and forming metal contact is disclosed. Solar cell contact and wiring is formed by depositing a thin film stack of a first metal material and a second metal material as an initiation layer or seed layer for depositing a bulk metal layer in conjunction with additional sheet processing, photolithography, etching, cleaning, and annealing processes. In one embodiment, the thin film stack for forming metal silicide with reduced contact resistance over the sheet is deposited by sputtering or physical vapor deposition. In another embodiment, the bulk metal layer for forming metal lines and wiring is deposited by sputtering or physical vapor deposition. In an alternative embodiment, electroplating or electroless deposition is used to deposit the bulk metal layer.

It is an object to reduce characteristic variation among transistors and reduce contact resistance between an oxide semiconductor layer and a source electrode layer and a drain electrode layer, in a transistor where the oxide semiconductor layer is used as a channel layer. In a transistor where an oxide semiconductor is used as a channel layer, at least an amorphous structure is included in a region of an oxide semiconductor layer between a source electrode layer and a drain electrode layer, where a channel is to be formed, and a crystal structure is included in a region of the oxide semiconductor layer which is electrically connected to an external portion such as the source electrode layer and the drain electrode layer.

A semiconductor light emitting device includes a semiconductor light emitting portion having a first contact layer of a first conductivity, a second contact layer of a second conductivity and an active layer sandwiched between the first and second contact layers. The device further includes a transparent electrode which substantially entirely covers a surface of the second contact layer in ohmic contact with the surface of the second contact layer and is transparent to a wavelength of light emitted from the semiconductor light emitting portion, and a metal reflection film which is opposed to substantially the entire surface of the transparent electrode and electrically connected to the transparent electrode, and reflects the light emitted from the semiconductor light emitting portion and passing through the transparent electrode toward the semiconductor light emitting portion.

A plurality of solar cells is connected together in a shingled fashion. Each of the solar cells includes grid wires that are attached to an electrode of the solar cell so as to receive charge carriers produced when photons are absorbed by the solar cell. The grid wires are then interconnected with adjacent solar cells when the solar cells are shingled together. The grid wires may be applied to the solar cells via a laminate and the electrical interconnection of the grid wires may be achieved by the use of a conductive epoxy.

An electrode for contacting an electrically conductive surface of a photovoltaic element includes an electrically insulating optically transparent film, an adhesive layer provided on a planar surface of the film, and a plurality of substantially parallel, electrically conductive wires embedded into the adhesive layer. The plurality of wires lies over the planar surface of the film. A part of the surfaces of the wires protrude from the adhesive layer. At least the part of the surfaces protruding from the adhesive layer are covered by a coating consisting of an alloy having a low melting point to solder the wires to the electrically conductive surface and to a first terminal bar. The adhesive layer has a thickness less that a thickness of the wires embedded therein.

A magnetron sputter reactor (410) and its method of use, in which SIP sputtering and ICP sputtering are promoted is disclosed. In another chamber (412) an array of auxiliary magnets positioned along sidewalls (414) of a magnetron sputter reactor on a side towards the wafer from the target is disclosed. The magnetron (436) preferably is a small one having a stronger outer pole (442) of a first polarity surrounding a weaker inner pole (440) of a second polarity all on a yoke (444) and rotates about the axis (438) of the chamber using rotation means (446, 448, 450). The auxiliary magnets (462) preferably have the first polarity to draw the unbalanced magnetic field (460) towards the wafer (424), which is on a pedestal (422) supplied with power (454). Argon (426) is supplied through a valve (428). The target (416) is supplied with power (434).

A probe pin for testing electric characteristics of a semiconductor device comprises a silicon pin core (3, 23, 33), and a conductive film (4, 24, 34) covering the entire surface, including the bottom face, of the pin core. The bottom face of the probe pin is connected directly to an electrode (7, 37) positioned in or on a print wiring board. A number of probe pins can be connected to the associated electrodes at a high density, thereby forming a fine-pitch probe card having a superior high-frequency signal characteristic.

The present invention provides a protection circuit disposed in a lithium-ion cell for protection of the lithium-ion cell. The protection circuit includes a first protection module, a second protection module, an integrated circuit module, a thermal sensor or thermocouple, a switch, a fuse and / or a resistor.

A new class of high-density, vertical Fin-FET devices that exhibit low contact resistance is described. These vertical Fin-FET devices have vertical silicon “fins” (12A) that act as the transistor body. Doped source and drain regions (26A, 28A) are formed at the bottoms and tops, respectively, of the fins (12A). Gates (24A, 24B) are formed along sidewalls of the fins. Current flows vertically through the fins (12A) between the source and drain regions (26A, 28A) when an appropriate bias is applied to the gates (24A, 24B). An integrated process for forming pFET, nFET, multi-fin, single-fin, multi-gate and double-gate vertical Fin-FETs simultaneously is described.

A rechargeable battery includes an electrode group for producing electricity, a case for housing the electrode group, a cap plate combined with the case, an electrode terminal electrically coupled to the electrode group, and a fixing member disposed inside the case and combined to the support shaft portion. The electrode terminal includes a head portion disposed outside the case, and a support shaft portion protruding from the head portion and penetrating the cap plate. Contact resistance of the rechargeable battery can be reduced with this configuration. A battery module includes a plurality of rechargeable batteries and bus bars electrically connecting at least two of the rechargeable batteries, wherein each rechargeable battery includes a case with an internal space, a cap plate combined with the case, an electrode terminal including a head portion caught on the cap plate and a support shaft portion protruding from the head portion and penetrating the cap plate, and a fixing member disposed inside the case and combined to the support shaft portion.

A contact plug structure formed on a contact hole of an insulating layer of a semiconductor device includes a metal silicide layer formed on a bottom part of the contact hole of the insulating layer, a manganese oxide layer formed on the metal silicide layer in the contact hole, and a buried copper formed on the manganese oxide layer which substantially fills the contact hole.

The invention discloses electric conductive silver paste and a manufacturing method of the electric conductive silver paste. The electric conductive silver paste comprises, by mass percentage, 35 - 65 % of micron-sized silver powder, 1-10 % of nanometer-sized silver powder of or 1-20 % of nanometer-sized silver and other metal alloy powder, and 1-10 % of an organic carrier; for ceramics, solar cell silver paste comprises 2-15 % of unleaded glass powder, each component is manufactured in parts, weighed, mixed and stirred or mixed and rapidly scattered, and ultrasonic-vibrated or fine adjusted of viscosity of solvent, and therefore the electric conductive silver paste is obtained. Due to the fact that the nanometer-sized silver powder or the nanometer-sized silver alloy powder is mixed with the micron-sized silver powder, intensity of conductivity and a circuit is improved, adhesive force of crushing resistance and a base plate is improved, at the same time unleaded slurry good in thixotropy, low in contacting resistance and low in piece-needed slurry amount replaces lead slurry materials, the electric conductive silver paste is used for manufacturing crystalline silicon solar cells, improves photoelectric conversion efficiency, accords with environmental-protection ideas, and can be produced in large scales continuously.

Provided are semiconductor devices having low resistance contacts and methods of manufacturing the same. One or more of the semiconductor devices include a substrate having first and second active regions; a P-channel field-effect transistor associated with the first active region and including at least one of the source and drain regions; a N-channel field-effect transistor associated with the second active region and including at least one of the source and drain regions; a first contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the P-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; a second contact pad layer comprising silicon (Si) and SiGe epitaxial layers on the at least one of the source and drain regions of the N-channel field-effect transistor, the SiGe epitaxial layer being sequentially stacked on the Si epitaxial layer; an interlayer insulating film formed on the P-channel and the N-channel field-effect transistors and including first and second contact holes, wherein the first contact hole includes a first lower region that exposes the SiGe epitaxial layer of the first contact pad layer and the second contact hole includes a second lower region that penetrates through the SiGe epitaxial layer of the second contact pad layer to expose the Si epitaxial layer of the second contact pad layer; first and second metal silicide films formed respectively in the first and second lower regions of the contact holes; and contact plugs formed on the first and second metal silicide films and filled in the first and second contact holes.

There is provided a semiconductor device wherein at least the largest width of a source / drain region is larger than the width of a semiconductor region and the source / drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.

A display device in which interconnection—electrode comprising a Cu alloy film having a lower electrical resistivity than Al alloy and a transparent conductive film are directly connected not by way of a refractory metal thin film, wherein the Cu alloy film contains Zn and / or Mg in a total amount from 0.1 to 3.0 at %, or Ni and / or Mn in a total amount from 0.1 to 5 at %, thereby enabling the direct connection at low resistivity between the Cu alloy film and the transparent electrode without using a barrier metal, and giving high display quality in a case of application, for example, to a liquid crystal display.

A method for forming a contact to a semiconductor fin which can be carried out by first providing a semiconductor fin that has a top surface, two sidewall surfaces and at least one end surface; forming an etch stop layer overlying the fin; forming a passivation layer overlying the etch stop layer; forming a contact hole in the passivation layer exposing the etch stop layer; removing the etch stop layer in the contact hole; and filling the contact hole with an electrically conductive material.

Engineered structure for charge storage. An electrolyte is disposed between two electrically conducting plates, each plate serving as a base for an aligned array of electrically conducting nanostructures extending from the surface of each plate into the electrolyte. The nanostructures have diameter and spacing comparable to the dimension of an ion of the electrolyte. An electrically insulating separator is disposed between the two plates. A CVD process (or other processes yielding similar results) is used to make the aligned array of electrically conducting nanostructures.

A vertical tunneling FET (TFET) provides low-power, high-speed switching performance for transistors having critical dimensions below 7 nm. The vertical TFET uses a gate-all-around (GAA) device architecture having a cylindrical structure that extends above the surface of a doped well formed in a silicon substrate. The cylindrical structure includes a lower drain region, a channel, and an upper source region, which are grown epitaxially from the doped well. The channel is made of intrinsic silicon, while the source and drain regions are doped in-situ. An annular gate surrounds the channel, capacitively controlling current flow through the channel from all sides. The source is electrically accessible via a front side contact, while the drain is accessed via a backside contact that provides low contact resistance and also serves as a heat sink. Reliability of vertical TFET integrated circuits is enhanced by coupling the vertical TFETs to electrostatic discharge (ESD) diodes.