324results about How to "High capacitance" patented technology

Engineered structure for charge storage. An electrolyte is disposed between two electrically conducting plates, each plate serving as a base for an aligned array of electrically conducting nanostructures extending from the surface of each plate into the electrolyte. The nanostructures have diameter and spacing comparable to the dimension of an ion of the electrolyte. An electrically insulating separator is disposed between the two plates. A CVD process (or other processes yielding similar results) is used to make the aligned array of electrically conducting nanostructures.

Non-volatile memory devices and a method thereof are provided. A non-volatile memory device according to an example embodiment of the present invention may include a first transistor including a source, a drain, and a control gate, a first storage node coupled to the first transistor, the first storage node configured to store information in a first manner, a first diode having a first end connected to the source of the transistor, the first diode configured to rectify a flow of current from the source of the transistor and a second storage node connected to a second end of the first diode, the second storage node configured to store information in a second manner. Another non-volatile memory device according to another example embodiment of the present invention may include a semiconductor substrate having a first conductivity type including an active region defined by a device isolating layer, a source region and a drain region formed by doping an impurity having a second conductivity type in the active region, a control gate electrode insulated from the active region, the control gate electrode extending across the active region disposed between the source region and the drain region, a first storage node layer interposed between the active region and the control gate electrode configured to store information in a first manner, a second storage node layer disposed on the source region configured to store information in a second manner and a diode interposed between the source region and the second storage node layer to rectify a flow of current to the source region. The example method may be directed to obtaining a higher storage capacity per cell area in either of the above-described example non-volatile memory devices.

Method of producing Ta powder for tantalum solid electrolytic capacitor capable of stably providing CV value of more than 220 k and to provide the Ta powder and its Ta granulated powder. In method of producing Ta powder by vaporizing TaCl5 through heating and reducing with H2 gas, the reduction is performed under conditions that feeding rate of TaCl5 vapor passing through section area of reaction field of 1 cm2 for 1 minute is 0.05˜5.0 g / cm2·min and residence time of TaCl5 vapor in the reduction reaction field is 0.1˜5 seconds and reduction temperature of TaCl5 is 1100˜1600° C., whereby Ta powder including a single phase of β-Ta of tetragonal system or mixed phase of β-Ta and α-Ta of cubic system and having average particle size of 30˜150 nm is obtained. Further, Ta granulated powder is obtained by granulating the Ta powder.

Disclosed is a multilayer insulator, a metal-insulator-metal (MIM) capacitor with the same, and a fabricating method thereof. The capacitor includes: a first electrode; an insulator disposed on the first electrode, the insulator including: a laminate structure in which an aluminum oxide (Al2O3) layer and a hafnium oxide (HfO2) layer are laminated alternately in an iterative manner and a bottom layer and a top layer are formed of the same material; and a second electrode disposed on the insulator.

A substrate processing apparatus enable fouling due to deposit to be monitored in real time. To monitor deposit attached to an inner wall surface of a processing chamber in which processing is carried out on a substrate, a deposit monitoring apparatus of the substrate processing apparatus includes a sensor for measuring a capacitance between two conductors spaced apart from each other and both connected to the sensor. The capacitance between the conductors increases with increase in an mount of deposit and reflects the state of fouling due to deposit.

A multilayer capacitor array having a plurality of multilayer capacitor devices formed in a single multilayer structure, the multilayer capacitor array including: a capacitor body formed by depositing a plurality of dielectric layers and having first and second side surfaces opposite to each other; a plurality of first polarity internal electrodes and second polarity internal electrodes, disposed oppositely to each other in the capacitor body, interposing the dielectric layer there between, and formed of a single electrode plate comprising a single lead, respectively; and a plurality of first polarity external electrodes and second polarity external electrodes, formed on the first side surface and second side surface, respectively, and connected to a correspondent polarity internal electrode via the lead, the first polarity external electrode formed on the first side surface and the second polarity external electrode formed on the second side surface, wherein the numbers of the first polarity external electrodes and the second polarity external electrodes are two or more, respectively, and are identical to each other, and a total number of the multilayer capacitor devices in the multilayer capacitor array is identical to the number of the first polarity external electrodes.