8978results about "Fixed capacitor dielectric" patented technology

A hybrid film, comprising a first polymer film having a plasma-treated surface and a second polymer film having first and second surfaces, with the first surface of the second polymer film being disposed along the first plasma-treated surface of the first polymer film, has superior thermal and mechanical properties that improve performance in a number of applications, including food packaging, thin film metallized and foil capacitors, metal evaporated magnetic tapes, flexible electrical cables, and decorative and optically variable films. One or more metal layers may be deposited on either the plasma-treated surface of the substrate and / or the radiation-cured acrylate polymer A ceramic layer may be deposited on the radiation-cured acrylate polymer to provide an oxygen and moisture barrier film. The hybrid film is produced using a high speed, vacuum polymer deposition process that is capable of forming thin, uniform, high temperature, cross-liked acrylate polymers on specific thermoplastic or thermoset films. Radiation curing is employed to cross-link the acrylate monomer. The hybrid film can be produced in-line with the metallization or ceramic coating process, in the same vacuum chamber and with minimal additional cost.

A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of internal electrode elements and a plurality of internal anchor tabs. Portions of the internal electrode elements and anchor tabs are exposed along the periphery of the electronic component in one or more aligned columns. Each exposed portion is within a predetermined distance from other exposed portions in a given column such that bridged terminations may be formed by depositing one or more plated termination materials over selected of the respectively aligned columns. Internal anchor tabs may be provided and exposed in prearranged relationships with other exposed conductive portions to help nucleate metallized plating material along the periphery of a device. External anchor tabs or lands may be provided to form terminations that extend to top and / or bottom surfaces of the device. Selected of the conductive elements may be formed by a finite volume percentage of ceramic material for enhanced durability, and external lands may be thicker than internal conductive elements and / or may also be embedded in top and / or bottom component surfaces. A variety of potential internal electrode configurations are possible including ones configured for orientation-insensitive component mounting and for high density peripheral termination interdigitated capacitors.

Tunable dielectric materials including an electronically tunable dielectric ceramic and a low loss glass additive are disclosed. The tunable dielectric may comprise a ferroelectric perskovite material such as barium strontium titanate. The glass additive may comprise boron, barium, calcium, lithium, manganese, silicon, zinc and / or aluminum-containing glasses having dielectric losses of less than 0.003 at 2 GHz. The materials may further include other additives such as non-tunable metal oxides and silicates. The low loss glass additive enables the materials to be sintered at relatively low temperatures while providing improved properties such as low microwave losses and high breakdown strengths.

A multilayer electronic component includes a plurality of dielectric layers interleaved with a plurality of first and second polarity electrode layers. Internal and / or external anchor tabs may also be selectively interleaved with the dielectric layers. Portions of the electrodes and anchor tabs are exposed along the periphery of the electronic component in respective groups and thin-film plated deposition is formed thereon by electroless and / or electrolytic plating techniques. A solder dam layer is provided over a given component surface and formed to expose predetermined areas where solder barrier and flash materials may be deposited before attaching solder preforms. Some embodiments include plated terminations substantially covering selected component surfaces to facilitate with heat dissipation and signal isolation for the electronic components.

A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.

A feedthrough terminal assembly for an active implantable medical device utilizes an insert to establish a reliable electrical connection between capacitor electrode plates, via inner surface metallization of a capacitor aperture, and an associated terminal pin 10, which passes at least partially therethrough. The inserts are preferably resiliently flexible, such as a spring, to establish this connection. The insert also serves to establish a mechanical connection between the capacitor and the terminal pin.

Improved termination features for multilayer electronic components are disclosed. Monolithic components are provided with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. The subject plated terminations are guided and anchored by exposed internal electrode tabs and additional anchor tab portions which may optionally extend to the cover layers of a multilayer component. Such anchor tabs may be positioned internally or externally relative to a chip structure to nucleate additional metallized plating material. External anchor tabs positioned on top and bottom sides of a monolithic structure can facilitate the formation of wrap-around plated terminations. The disclosed technology may be utilized with a plurality of monolithic multilayer components, including interdigitated capacitors, multilayer capacitor arrays, and integrated passive components. A variety of different plating techniques and termination materials may be employed in the formation of the subject self-determining plated terminations.

This invention provides novel capacitors comprising nanofiber enhanced surface area substrates and structures comprising such capacitors, as well as methods and uses for such capacitors.

A terminal to, most commonly, a ceramic capacitor, most commonly a multilayer ceramic capacitor (MLCC), is formed by electroless plating, also known as electroless deposition or simply as electrodeposition. In the MLCC having a multiple parallel interior plates brought to, and exposed at, at least one, first, surface, an electrically-conductive first-metal layer, preferably Cu, is electrolessly deposited upon this first surface directly in contact with, mechanically connected to, and electrically connected to, the edges of these interior plates. Lateral growth of the electrolessly-deposited first-metal is sufficient to span from exposed plate to exposed plate, electrically connecting the plates. One or more top layers, preferably one of Ni and one of Sn and Pb, are deposited, preferably by plating and more preferably by electrolytic plating, on top of the electrolessly-deposited Cu.

A circuit board structure with embedded electronic components includes: a carrier board having an adhesive layer with two surfaces formed with first and second metal oxide layers covered by first and second metal layers and having at least one through hole; at least one semiconductor chip received in the through hole of the carrier board; an adhesive material filling a gap between the through hole and the semiconductor chip so as to secure the semiconductor chip in position to the through hole; a high dielectric material layer formed outwardly on the second metal layer; and at least one electrode board formed outwardly on the high dielectric material layer such that a capacitance component is formed with the second metal layer, high dielectric material layer, and electrode board. Accordingly, the capacitance component is integrated into the circuit board structure.