136 results about "Loop inductance" patented technology

A bus system is disclosed for use with switching devices, such as power electronic devices. The system includes generally parallel bus elements that define electrical reference planes, such as for a dc bus. The bus elements are separated from one another by insulative layers, with additional insulative layers being available for separating the system from other circuit components. Portions of the bus elements are extended or exposed to permit connection to the circuit elements, including packaged switching circuits and energy storage or filtering circuits. The bus system may be conformed to a variety of geometric configurations, and substantially reduces parasitic inductance and total loop inductance in the resulting circuitry.

Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 is constituted by providing a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

Chip capacitors 20 are provided in a printed circuit board 10. In this manner, the distance between an IC chip 90 and each chip capacitor 20 is shortened, and the loop inductance is reduced. In addition, the chip capacitors 20 are accommodated in a core substrate 30 having a large thickness. Therefore, the thickness of the printed circuit board does not become large.

A radio frequency (“RF”) harmonic filter circuit as disclosed herein is fabricated using integrated passive device (“IPD”) technology. The RF harmonic filter circuit is configured to provide second, third, and fourth harmonic rejection while providing good input and output impedance matching. The RF harmonic filter circuit employs only one IPD loop inductance (preferably used for a second harmonic resonance circuit), which results in a significant die / package size reduction. The RF harmonic filter circuit also employs a combined circuit that performs input and / or output impedance matching and third harmonic rejection.

An amplifier and method for improving linear response includes a plurality of N bi-SQUIDs. Each bi-SQUID has a non-uniform bi-SQUID parameter βi, described by βi=2πLiIciΦ0 can be defined for each bi-SQUIDs from i=1 to N, where Li is the loop inductance, ic is the critical current, and Φ0 is a flux quantum for each bi-SQUID. The non-uniform bi-SQUIDs can be connected in series or in parallel to establish a Superconducting Quantum Interference Filter (SQIF) array of bi-SQUIDs. Once connected, a mutual inductance between the connected bi-SQUIDs can be established. If the mutual inductance between connected bi-SQUIDs is accounted for, careful manipulation of the critical current or the loop size, or both, of each bi-SQUID can result in extremely uniform behavior (linear response) of the SQIF when considered as a whole, even though the behavior of the element bi-SQUIDs is non-uniform (different βi, parameters).

A line narrowed gas discharge laser system and method of operation are disclosed which may comprise: an oscillator cavity; a laser chamber comprising a chamber housing containing a lasing medium gas; at least one peaking capacitor electrically connected to the chamber housing and to a first one of a pair of electrodes; a second one of the pair of electrodes connected to an opposite terminal of the at least one peaking capacitor; a current return path connected to the chamber housing; the one terminal, the first one of the electrodes, the lasing medium gas, the second one of the electrodes, the current return path and the second terminal forming a head current inductive loop having an inductance unique to the particular head current inductive loo; a spectral quality tuning mechanism comprising a mechanism for changing the particular head current inductive loop inductance value for the particular head current inductance loop.

A chip capacitor 20 is provided in a core substrate 30 of a printed circuit board 10. This makes it possible to shorten a distance between an IC chip 90 and the chip capacitor 20 and to reduce loop inductance. Since the core substrate 30 id constituted by provided a first resin substrate 30a, a second resin substrate 30b and a third resin substrate 30c in a multilayer manner, the core substrate 30 can obtain sufficient strength.

A radio frequency (“RF”) harmonic filter circuit as disclosed herein is fabricated using integrated passive device (“IPD”) technology. The RF harmonic filter circuit is configured to provide second, third, and fourth harmonic rejection while providing good input and output impedance matching. The RF harmonic filter circuit employs only one IPD loop inductance (preferably used for a second harmonic resonance circuit), which results in a significant die / package size reduction. The RF harmonic filter circuit also employs a combined circuit that performs input and / or output impedance matching and third harmonic rejection.

An efficient inductance modeling approach for on-chip power-ground wires using their effective self-loop-inductances is disclosed. Instead of extracting the inductive coupling between every two parallel wires and putting this huge number inductance elements into circuit simulation, this technique determines the effective self-loop-inductance for each power or ground wire segment and only generates a circuit with these effective self-inductors for simulation. This approach greatly reduces the circuit size and makes the full-chip power-ground simulation with the consideration of inductance feasible.

Discontinuous loop antennas and related components, radio-frequency identification (RFID), tags, systems, and methods are disclosed. A discontinuous loop antenna is an antenna loop structure that includes a discontinuity portion. The discontinuous loop antenna can be coupled to an RFID chip to provide an RFID tag. The discontinuity portion decreases the loop inductance and tag capacitance, thus enabling the discontinuous loop antenna to have significantly larger loop area while still matching the chip impedance, resulting in dramatic increases in near-field sensitivity. Increased near-field sensitivity provides increased power harvesting efficiency during near-field coupling. As one non-limiting example, an RFID tag having a discontinuous loop antenna may achieve significantly more power harvesting from a RF signal than an RFID tag having a continuous loop antenna tuned to the same or similar resonant frequency. The discontinuity portion can be trimmed after fabrication allowing the resonant frequency of the RFID tag to be tuned.

Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are arranged to reduce the loop inductance of corresponding signal and power supply bond wires.

A bus system is disclosed for use with switching devices, such as power electronic devices. The system includes generally parallel bus elements that define electrical reference planes, such as for a dc bus. The bus elements are separated from one another by insulative layers, with additional insulative layers being available for separating the system from other circuit components. Portions of the bus elements are extended or exposed to permit connection to the circuit elements, including packaged switching circuits and energy storage or filtering circuits. The bus system may be conformed to a variety of geometric configurations, and substantially reduces parasitic inductance and total loop inductance in the resulting circuitry.

The invention discloses a design method of a miniaturization label buckling antenna of a tire embedded radio frequency identification device (RFID). The design method comprises the following steps of determining geometric dimension of bending units and input impedance of a label chip; determining quantity of the bending units in the horizontal direction; determining quantity of the bending units in the vertical direction; adjusting width of a meander line to enable antenna gain to be maximum; and increasing feed ends and adjusting loop inductance to enable the antenna impedance to be in conjugate match with the chip impedance. The design method is simple, effective and convenient to design, has good impedance matching characters, and enables the miniaturization label buckling antenna to be maximum in radiation gain and low in cost. Simultaneously, the design method can be applied to RFID application fields of communication, industrial control, equipment manufacturing, intelligent agriculture, food safety and the like.

Disclosed is a method and structure for locally powering a semiconductor chip within a package. The structure and method incorporate a local voltage regulator mounted adjacent a semiconductor chip on a top surface of a carrier. The voltage regulator is electrically connected to a power plane disposed within the carrier. The voltage regulator continuously senses the reflected voltage of the power plane at a regulated output port and actively cancels time domain noise within its operational bandwidth. Mounting the voltage regulator on top of the carrier adjacent to the chip minimizes loop inductance between the regulator and power plane and also minimizes delay caused by impedance of the power plane on the current flowing to the chip.

The invention relates to a compact type fast pulse discharging unit, which comprises a first pulse capacitor, a second pulse capacitor, a three-electrode gas switch, guiding connectors and an insulated support frame, wherein the first pulse capacitor and the second pulse capacitor are fixedly arranged on the insulated support frame; the three-electrode gas switch is fixedly arranged between the first pulse capacitor and the second pulse capacitor; and the first pulse capacitor, the second pulse capacitor and the three-electrode gas switch are fixedly connected to each other through cylindrical electrodes of the pulse capacitors and upper and lower guiding connectors of the three-electrode gas switch. The compact type fast pulse discharging unit has the advantages of high output voltage, compact structure, small loop inductance and the like, and can meet the demand on outputting a fast rise time high-power pulse.

A cable reduces loop inductance by changing the cross-sectional shape of the conductive elements of power supply and return conductors to something other than the traditional circular cross sectional shape, e.g., to a thin generally rectangular shape. The power supply and return conductors are also controlled in placement along the length of the cable, so that mutual inductance is maximized within a given power supply circuit, and minimized between the given power supply circuit and other power supply circuits within the cable. The return power supply conductor may optionally be sized for multiple power supply circuits, which may further reduce loop inductance and reduce crosstalk noise between different power supply circuits within a common cable. The power supply and return conductors may be part of a hybrid cable used to power and communicate with plural remote radio units proximate a top of a tower.

A method and apparatus that provides improved loop inductance of decoupling capacitors. Vias are moved close to the pads and close to each other. Instead of placing power and ground vias on opposite sides of the capacitor, these vias are moved around to the same side of the capacitor and are placed as close to each other as manufacturing tolerances will allow. For designs using standard two-terminal surface mount capacitors, two vias per capacitor, and standard manufacturing procedures (no vias inside pads, for example), the lowest possible loop inductance of the capacitor's connections to the printed circuit board planes is provided. This results in the lowest effective capacitor series input inductance.

A bus system is disclosed for use with switching devices, such as power electronic devices. The system includes generally parallel bus elements that define electrical reference planes, such as for a dc bus. The bus elements are separated from one another by insulative layers, with additional insulative layers being available for separating the system from other circuit components. Portions of the bus elements are extended or exposed to permit connection to the circuit elements, including packaged switching circuits and energy storage or filtering circuits. The bus system may be conformed to a variety of geometric configurations, and substantially reduces parasitic inductance and total loop inductance in the resulting circuitry.

The invention relates to the field of busbars in the electric technology, in particular to an L-shaped split type composite busbar which comprises a lower split composite busbar and an upper split composite busbar. The lower split composite busbar is formed by three layers of L-shaped busbars in an identical-direction-overlaying mode. The upper split composite busbar is formed by two layers of flat busbars in an overlaying mode. The position between two adjacent busbars is filled with insulation materials. A connector for being connected with a circuit device is arranged on the lower split composite busbar. An alternating output terminal is led out from one layer of L-shaped busbar of the lower split composite busbar. The L-shaped split type composite busbar replaces a direct-current bus, loop inductance is lowered, the reliability of IGBT working is improved, main circuit cable connecting is replaced, layout is easy, quality is reliable, the size and the weight of a system are reduced, and maintaining on a main circuit is convenient.

The present disclosure provides a hybrid circuit breaker having a bridge induction transfer structure, characterized in that the circuit breaker comprises a main current circuit, an over-voltage limiting circuit, and a transfer current circuit; and the main current circuit, the over-voltage limiting circuit, and the transfer current circuit are connected in parallel. The induction transfer circuit in the transfer current circuit comprises an induction transfer inductor, an induction transfer capacitor, and an induction transfer branch power semiconductor device which are connected in series; the transfer current circuit further comprises a bridge circuit comprised of a main loop capacitor; the main loop inductor and the induction transfer inductor are coupled to form a transformer. The present invention can implement fast breaking of the current, and effectively reduce the volume and manufacturing cost of the circuit breaker. With the induction transfer circuit, fast current transfer is implemented. The main loop capacitor needs no pre-charging. Isolation between the secondary charging circuit and the main loop is implemented. The transfer speed is fast, and the breaking reliability is high.

The invention discloses a three-phase inversion composite busbar suitable for a half-bridge module. The three-phase inversion composite busbar comprises three flat busbar bodies which are stacked together. The three busbar bodies comprise the positive busbar body, the negative busbar body and the M busbar body in sequence from back to front. A high-insulating-strength material is arranged between every two adjacent busbar bodies. The busbar bodies are provided with discharge resistor connection portions, input end connection portions, IGBT connection portions, absorption capacitor connection portions and supporting capacitor terminals, wherein the discharge resistor connection portions, the input end connection portions, the IGBT connection portions, the absorption capacitor connection portions and the supporting capacitor terminals are used for being connected with direct current input ends or circuit devices. The three-phase inversion composite busbar effectively decreases the loop inductance, lowers the peak voltage generated when overvoltage occurs, improve the work reliability of an IGBT, makes a main circuit convenient to connect and maintain, simple in layout and more reliable in quality, decreases the size and the weight of a system and meets the development requirements for heavy load and high density of haulage motors. The parasitic inductance of the three-phase inversion composite busbar can be smaller than 50 nH, and the three-phase inversion composite busbar can insulate and resist 3500 V voltage of an alternating current.

A compact high-power pure-sinewave inverter amenable to mass manufacturing techniques. Methods for increasing the power rating, power density and / or power conversion efficiency of a sinewave-modulated pulse-width-modulated (PWM) inverter having a either half-bridge or full-bridge topology, including minimizing uncoupled inductances and loop inductances in the primary winding(s) by employing either ribbon-like conductors having a high crossectional aspect ratio or litz-wire. A compact linear heatsink adapted to cool a row of semiconductor devices (such as inverter switches) mounted on a high-current printed circuit board. Methods for inexpensive manufacture of a fluid-cooled linear heat sink. A transformer including a filter inductor core.

A semiconductor package includes a semiconductor device including a plurality of signal pads and a plurality of auxiliary pads which are alternatively arranged in a predetermined direction, and a package board including a plurality of signal bond fingers, a plurality of first power supply voltage bond fingers, and a plurality of second power supply voltage bond fingers. The signal pads are connected respectively to the signal bond fingers by first wires. The first power supply voltage bond fingers and the second power supply voltage bond fingers are connected respectively to the auxiliary pads by second wires. The first wires are disposed between those of the second wires which are connected to the first power supply voltage bond fingers and those of the second wires which are connected to the second power supply voltage bond fingers.

A probe card is disclosed, which has a conductive layer additionally provided on an insulating seat of a probe stand and the conductive layer is electrically connected to a ground circuit on the probe card via a conductive pin being fed through the insulating seat. A conductive wire is wound surrounding the intermediate segment of the probe, one end of the conductive wire is electrically connected to the ground circuit of the circuit board, and the other end of the conductive wire is electrically connected to the conductive layer of the probe stand. Thus, due to that an additional ground portion of the conductive layer is provided on the conductive wire wound surrounding the probe, a loop inductance of the probe in the insulating seat can be reduced such that accuracy of test data of the probe can be enhanced.

Embodiments provide for integrated circuit chip and device having such an integrated circuit, in which different types of pads are arranged in separate rows. In one embodiment the pads are intelligently arranged to reduce the loop inductance of corresponding signal and power supply bond wires.

The invention discloses a design method of a direct-current ice melting device with a special converter transformer. The design method comprises the following steps: 1) determining a covering path of the ice melting device; 2) pre-selecting ice melting current of a lead wire; 3) determining maximal allowed current of the lead wire; 4) calculating direct-current voltage drop and power under the pre-selected ice melting current; 5) determining rated parameters of the ice melting device; 6) calculating ideal no-load direct-current voltage; 7) calculating commutation reactor valve side rated voltage; 8) calculating converter transformer and commutation reactor side rated voltages; 9) calculating converter alternating-current side rated current; 10) calculating inductance of the commutation reactor; 11) calculating rated capacity of the converter transformer; 12) calculating inductive impedance of the converter transformer; 13) determining rated capacity and current of a TCR (Thyristor Controlled Reactor) or TSR (Thyristor Switched Reactor) branch circuit; 14) determining total inductive impedance value of the TCR or TSR branch circuit; 15) determining inductance value needed to be increased of the TCR or TSR branch circuit; 16) determining zero-power loop inductance; 17) determining zero-power minimal allowed current; and 18) designing an alternating-current filter.

The multichannel harmonic suppressor with inductance coil and capacitor of low voltage and power belongs to power network control device and overcomes the shortcoming in existing technique to decrease cost and volume and satisfy require for high voltage and current. Wherein, joining the product in series with power network bus-bar, arranging i winding coils on sub converter connected to inductance coil and capacitor in series to constitute series resonant circuit of inductance and capacitor, wherein, it should be ªÏL=1 / ªÏC for working frequency ªÏ; all the inductance value and capacitor value equals, so does the number of turns and geometric size. This invention is convenient to maintenance.

A line narrowed gas discharge laser system and method of operation are disclosed which may comprise: an oscillator cavity; a laser chamber comprising a chamber housing containing a lasing medium gas; at least one peaking capacitor electrically connected to the chamber housing and to a first one of a pair of electrodes; a second one of the pair of electrodes connected to an opposite terminal of the at least one peaking capacitor; a current return path connected to the chamber housing; the one terminal, the first one of the electrodes, the lasing medium gas, the second one of the electrodes, the current return path and the second terminal forming a head current inductive loop having an inductance unique to the particular head current inductive loop; a spectral quality tuning mechanism comprising a mechanism for changing the particular head current inductive loop inductance value for the particular head current inductance loop.