90results about How to "Small parasitic capacitance" patented technology

An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

The present invention discloses an asymmetric bidirectional silicon-controlled rectifier, which comprises: a second conduction type substrate; a first conduction type undoped epitaxial layer formed on the substrate; a first well and a second well both formed inside the undoped epitaxial layer and separated by a portion of the undoped epitaxial layer; a first buried layer formed in a junction between the first well and the substrate; a second buried layer formed in a junction between the second well and the substrate; a first and a second semiconductor area with opposite conduction type both formed inside the first well; a third and a fourth semiconductor area with opposite conduction type both formed inside the second well, wherein the first and second semiconductor areas are connected to the anode of the silicon-controlled rectifier, and the third and fourth semiconductor areas are connected to the cathode of the silicon-controlled rectifier.

A memory cell array is physically divided into an even number of sectors, with each pair of sectors sharing read circuitry. The outputs of the shared read circuitry are commonly connected to form data lines spanning the height of the array, which are input to global sense amplifiers. A two-stage sensing scheme is employed, with first stage and global sense amplifiers. The driving capability of the first stage sense amplifier can be used to decrease the time to charge or discharge the data lines, which reduces the total signal development time and consequently improves read performance. Granularity of the array can be adjusted by dividing groups and sub-groups of memory cells within a sector accordingly. In a read operation, the bit line in the opposite sector at the same column location is used as reference bit line, which greatly improves matching of bit line loading for the sensing.

The invention provides solutions to solve the power consumption of the image data buses of an LCD source driver. With a bus buffer provided in one embodiment of the invention, a first image data buses are divided into several groups. Each group of image data buses is dispatched by the bus buffer. It is possible in one embodiment of the invention that some groups are active when the others are passive. Therefore, unnecessary power consumption is cut off. Despite the power saved by the management of the bus buffer, the parasitic capacitance of each group of image data buses is much smaller than that of the image data buses in the prior art. Moreover, the management of the bus buffer can depend upon the layout patterns or the layout locations of circuit components so that the driving strength of the bus buffer may be modified according to the layout pattern or the layout locations.

A method is provided for fabricating a silicon (Si)-on-insulator (SOI) double-diffused metal oxide semiconductor transistor (DMOST) with a stepped channel thickness. The method provides a SOI substrate with a Si top layer having a surface. A thinned area of the Si top layer is formed, and a source region is formed in the thinned Si top layer area. The drain region is formed in an un-thinned area of the Si top layer. The channel has a first thickness adjacent the source region with first-type dopant, and a second thickness, greater than the first thickness, adjacent the drain region. The channel also has a sloped thickness between the first and second thicknesses. The second and sloped thicknesses have a second-type dopant, opposite of the first-type dopant. A stepped gate overlies the channel.

In terms of achieving a reduction in the cost of an antenna switch, there is provided a technology capable of minimizing harmonic distortion generated in the antenna switch even when the antenna switch is particularly formed of field effect transistors formed over a silicon substrate. Between the source region and the drain region of each of a plurality of MISFETs coupled in series, a distortion compensating capacitance circuit is coupled which has a voltage dependency such that, in either of the cases where a positive voltage is applied to the drain region based on the potential of the source region and where a negative voltage is applied to the drain region based on the potential of the source region, the capacitance decreases to a value smaller than that in a state where the potential of the source region and the potential of the drain region are at the same level.

An object is to provide a semiconductor device including a thin film transistor with excellent electrical characteristics and high reliability and a method for manufacturing the semiconductor device with high mass productivity. A main point is to form a low-resistance oxide semiconductor layer as a source or drain region after forming a drain or source electrode layer over a gate insulating layer and to form an oxide semiconductor film thereover as a semiconductor layer. It is preferable that an oxygen-excess oxide semiconductor layer be used as a semiconductor layer and an oxygen-deficient oxide semiconductor layer be used as a source region and a drain region.

An isolator is configured by a transmission circuit, a transformer, and a reception circuit. A first coil of the transformer is disposed on a back surface of a first semiconductor substrate; a transmission circuit and a second coil of the transformer are disposed on a front surface. The first coil is embedded within a coil trench, is led out through an embedded via-metal-film to a substrate front surface, and is electrically connected to the transmission circuit. The second coil is disposed on an insulating layer of the substrate front surface. The reception circuit is disposed on a front surface of a second semiconductor substrate. The second coil and the reception circuit are electrically connected to each other by connecting first and third electrode pads disposed respectively on the front surfaces of the first and second semiconductor substrates through wires.

A semiconductor device having: an underlie having a conductive region in the surface layer of the underlie; an insulating etch stopper film covering the surface of the underlie; an interlayer insulating film formed on the insulating etch stopper film; a wiring trench formed in the interlayer insulating film, the wiring trench having a first depth from the surface of the interlayer insulating film; a contact hole extending from the bottom surface of the wiring trench to the surface of the conductive region; and a dual damascene wiring layer embedded in the wiring trench and the contact hole, wherein the interlayer insulating film includes a first kind of an insulating layer surrounding the side wall and bottom surface of the wiring trench and a second kind of an insulating layer having etching characteristics different from the first kind of the insulating layer. The semiconductor device is provided which can protect the underlying conductive region sufficiently and has a dual damascene wiring layer having a high reliability and a small wiring capacitance.

System and method for increasing the frequency tuning range of a RF / microwave LC oscillator. A preferred embodiment comprises a voltage controlled oscillator (VCO) configured to generate an output signal at a frequency that is dependent upon a magnitude of an input voltage level and an effective inductance of an inductive load and a variable inductor coupled to the VCO. The variable inductor comprises a primary inductor coupled to the VCO to produce a magnetic field based upon a current flowing through the primary inductor and a secondary inductor magnetically coupled to the primary inductor, the secondary inductor to affect the magnitude of the effective inductance of the primary inductor.

A semiconductor device is formed in such a manner that a first insulator, a first oxide semiconductor, and a first conductor are formed; the first conductor is processed to form a second conductor; the first oxide semiconductor is processed to form a second oxide semiconductor; a second insulator is formed over the second conductor; a third insulator is formed over the second insulator; a fourth insulator is formed over the third insulator; the fourth insulator, the third insulator, the second insulator, and the second conductor are selectively processed to partly expose the second oxide semiconductor; a fifth insulator is formed over the second oxide semiconductor and the fourth insulator; and a third conductor is formed over the fifth insulator and then chemical mechanical polishing treatment is performed to expose a top surface of the fourth insulator.

In a BH laser which uses InGaAlAs-MQW in an active layer, Al-based semiconductor multi-layer films including an InP buffer layer and an InGaAlAs-MQW layer, and an InGaAsP etching stop layer are formed in a mesa shape, and a p type InP burial layer is buried in side walls of the mesa shape. An air ridge mesa-stripe of a lateral center that is substantially the same as that of the mesa shape is formed on the mesa shape. According to the present structure, a leakage current can be considerably reduced, the light confinement coefficient can be made to be larger than in a BH laser in the related art, and thereby it is possible to implement a semiconductor laser with a low leakage current and a high relaxation oscillation frequency.