197 results about "Cascode amplifier" patented technology

A multi-stage amplifier circuit arranged to take advantage of the desirable characteristics of non-field-plate and field plate transistors when amplifying a signal. One embodiment of a multi-stage amplifier according to the present invention comprises a non-field-plate transistor and a field-plate transistor. The field-plate transistor has at least one field plate arranged to reduce the electric field strength within the field plate transistor during operation. The non-field plate transistor is connected to the field plate transistor, with the non-field-plate providing current gain and the field plate transistor providing voltage gain. In one embodiment the non-field-plate and field plate transistors are coupled together in a cascode arrangement.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.

A low voltage amplifier with gain boosting and a reduced power supply voltage requirement. A cascode amplifier circuit, biased with the power supply voltage, amplifies a pair of related, differential input signals based upon a pair of gain boost control signals and in accordance therewith provides a pair of gain boosted signals which correspond to the input signals. A gain boost control circuit, also biased with the power supply voltage, uses the differential input signals to generate the gain boost control signals. A class AB amplifier circuit, also biased with the power supply voltage, amplifies the gain boosted signals and in accordance therewith provides a class AB output signal which corresponds to the original input signals. The cascode amplifier circuit, gain boost control circuit and class AB amplifier circuit together operate with a minimum power supply voltage which equals a sum of one active transistor input bias potential and two active transistor output bias potentials

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

Provided is a differential cascode voltage-controlled oscillator that can reduce a phase noise by the use of a quality factor enhancement technique with negative conductance and can mitigate a ground-caused noise effect by the use of a cascode connection technique. The differential cascode voltage-controlled oscillator includes an AC signal generator, and first through fourth cascode amplifiers. The AC signal generator generates an AC signal with a certain frequency according to a control voltage. The first cascode amplifier is connected in a cascode configuration, and amplifies the AC signal to output the resulting signal to a first output terminal. The second cascode amplifier is connected in a cascode configuration and connected to the first cascode amplifier in a cross-coupled configuration, to amplify the AC signal to output the resulting signal to a second output terminal. The third cascode amplifier is connected in a cascode configuration to amplify the AC signal to output the resulting signal to the first output terminal. The fourth cascode amplifier is connected in a cascode configuration and connected to the third cascode amplifier in a cross-coupled configuration, to amplify the AC signal to output the resulting signal to the second output terminal. Herein, the first and second cascode amplifiers and the third and fourth cascode amplifiers are symmetrically connected to differentially amplify the AC signal.

A differential cascode amplifier has first and second cascode circuits, driven by two differential signal sources including input resistances.The first cascode circuit includes a first input transistor having a first collector, a first emitter, and a first base, and a first output transistor having a second collector, a second base, and a second emitter coupled to the first collector. The second cascode circuit includes a second input transistor having a third collector, a third emitter, and a third base, and a second output transistor having a fourth collector, a fourth base, and a fourth emitter coupled to the third collector. The amplifier has a first connection connecting the first base to the fourth base, and a second connection connecting the second base to the third base.This cross-connected differential cascode architecture provides doubled output bandwidth and current gain (in dB), further increasing input impedance and output swing.

A low-noise amplifier circuit to convert a single-ended input into a dual-ended output includes an input transconductance stage circuit, including a first MOS transistor coupled in parallel with a second MOS transistor; a current buffer circuit, including a third MOS transistor coupled in parallel with a fourth MOS transistor; each of the first, second, third, and fourth transistors having a body, gate, source, and drain; the input transconductance stage circuit and the current buffer circuit being cascode coupled, forming a cascode amplifier configuration; the single-ended input being at the source of one of the first and second transistors in the input transconductance stage circuit; the dual-ended output being a differential output across the drain of the third transistor and the drain of the fourth transistor; the first and second transistors of the input transconductance stage circuit being cross-coupled, wherein the body of the first transistor is coupled to the source of the second transistor, and the body of the second transistor is coupled to the source of the first transistor; and the third and fourth transistors of the current buffer circuit being cross-coupled, wherein a first capacitance is coupled between the gate of the third transistor and the source of the fourth transistor, and a second capacitance is coupled between the gate of the fourth transistor and the source of the third transistor.

The invention provides an amplifying circuit for reducing electric power consumption at a standby mode time. Therefore, in DMOS and NMOS transistors constituting a cascode amplifier, the gate of the DMOS transistor of an initial stage is biased to a grounding voltage through a resistor, and the source of the DMOS transistor is connected to the output side of an inverter through an inductor. When a control signal is set to a level “H”, the output of the inverter becomes a level “L”, and the DMOS transistor attains a turning-on state and a sufficient operating electric current is flowed to the cascode amplifier. Thus, an input signal is amplified and is outputted as an output signal. In contrast to this, when the control signal is set to the level “L”, the output of the inverter becomes the level “H”, and the DMOS transistor attains a turning-off state and the operating electric current of the cascode amplifier is stopped.

A variable gain amplifier is provided that can obtain a wide range of gain variation and suppress the deterioration of linearity when switching between amplifying transistors. The variable gain amplifier includes a plurality of cascode amplifiers each including an amplifying transistor and a plurality of cascode transistors connected in a cascode arrangement to an output terminal of the amplifying transistor. The plurality of cascode amplifiers are connected through attenuators. The variable gain amplifier further includes a first controller that controls ON / OFF operations of the plurality of cascode transistors included in each cascode amplifier; and a second controller that controls ON / OFF operations of a plurality of amplifying transistors, only one of which is included in each of the plurality of cascode amplifiers, such that only selected one of the plurality of amplifying transistors is turned on.

A highly linear variable-gain low noise amplifier is a cascode amplifier. The cascode amplifier includes a gain control circuit, a load circuit, a current steering circuit and an input circuit. The gain control circuit is used for receiving a gain adjusting voltage, thereby generating a resistance adjusting signal and a current steering control signal. The load circuit includes plural variable resistors. The resistances of the variable resistors are adjusted according to the resistance adjusting signal. The current steering circuit is connected to the load circuit through plural current paths for adjusting a current ratio between the plural current paths according to the current steering control signal. The current steering circuit has differential signal output terminals. The input circuit is connected to the current steering circuit. The input circuit has differential signal input terminals.

An electronic circuit has an amplifier with an amplifying transistor and a cascode transistor. A capacitive voltage divider applies a fraction of an RF signal swing from the drain of the cascode transistor to the gate of the cascode transistor, the fraction being determined by a ratio between capacitance values. In addition a bias voltage supply circuit is provided. The bias voltage supply circuit is configured to define a relation between an average gate voltage of the cascode transistor and an average drain supply voltage at the drain of the cascode transistor. This relation increases the average gate voltage with increasing average drain voltage, and the relation provides a non zero average gate voltage when extrapolated to zero average drain supply voltage.

An electronic circuit includes transistors having first to third terminals, the third terminal controlling the current between the first terminal and the third terminal. The electronic circuit includes: a cascode amplifier (10) including an input transistor (Q1) receiving an input signal (IN) through the third terminal, and an output transistor (QO) having the first terminal connected to the second terminal of the input transistor (QI), the third terminal connected to the ground potential via a capacitor (C1) and the second terminal outputting therethrough an output signal; and a control circuit (20) including a control transistor receiving a control signal through the third terminal, and a diode connected to the first and second terminals of the control transistor (QC) in series. The third terminal of the output transistor (QO) of the cascode amplifier (10) is connected to the ground potential through the control transistor (QC) and the diode (D). The electronic circuit has a reduced signal switching time.

A variable gain amplifier is provided. The variable gain amplifier includes a first cascode amplifier which includes a first common source transistor and a first common gate transistor, a second cascode amplifier which forms a differential pair with the first cascode amplifier and includes a second common source transistor and a second common gate transistor, and a gain adjustment unit having a side connected to the drain of the first common source transistor and the source of the first common gate transistor and another side connected to the drain of the second common source transistor and the source of the second common gate transistor.