905results about How to "Reduce phase noise" patented technology

A clock recovery circuit through NFC active load modulation based on a digital phase-locked loop is formed by a digital phase-locked loop and a digital delay locking loop. The digital phase-locked loop works under a tracking carrier frequency mode and a fixed oscillation frequency mode. Under the fixed oscillation frequency mode, oscillation frequency is formed and locked in the period of tracking a carrier wave, the digital phase-locked loop is an all-digital structure phase-locked loop, and the digital delay locking loop receives a split phase clock of the phase-locked loop, and fast locks a clock which is closest to a carrier phase through comparison with a phase of the carrier wave. The digital delay locking loop works under a phase tracking mode and a fixed phase mode, under the fixed phase mode, the digital delay locking loop constantly outputs the same split phase clock, and the clock is obtained under a tracking mode. The clock recovery circuit reduces frequency difference caused by injecting noise in the time of conversion from a closed loop to an open loop, enables bandwidth of the phase-locked loop to be reduced to further lower phase noise, and can avoid the situation that the phase difference cannot be corrected due to the fact that the bandwidth is reduced.