2070 results about "Digital analog" patented technology

A method and apparatus for natural language interpretation are described. The invention includes a schema and apparatus for storing, in digital, analog, or other machine-readable format, a network of propositions formed of a plurality of text and / or non-text objects, and the steps of retrieving a string of input text, and locating all associated propositions in the network for each word in the input string. Embodiments of the invention also include optimization steps for locating said propositions, and specialized structures for storing them in a ready access storage area simulating human short-term memory. The schema and steps may also include structures and processes for obtaining and adjusting the weights of said propositions to determine posterior probabilities representing the intended meaning. Embodiments of the invention also include an apparatus designed to apply an automated interpretation algorithm to automated voice response systems and portable knowledge appliance devices.

An integrated voltage / current / power regulator / switch (VCPRS) system and method are disclosed in which regulator / switch circuitry is vertically integrated on top of an existing integrated circuit. The present invention does not require additional integrated circuit chip area for the regulator pass device as is required in the prior art, and by virtue of its construction provides a significantly reduced on-resistance as compared to all prior art implementations. The present invention both stabilizes the power supply for large area integrated circuits and permits individual areas of the integrated circuit to have switched power capability, a highly desirable feature in low power and battery power applications. The present invention permits an increase in the power supply rejection ratio (PSRR) for digital, analog, and especially mixed-signal integrated circuit designs by permitting various circuit blocks to have localized power regulation that is obtained from a common power supply plane within the integrated circuit framework. Finally, the present invention appears to be the only economically practical method of addressing the power supply regulation requirements of modern and future integrated microprocessor designs.

Within a digital acquisition device with a built in flash unit, the exposure of an acquired digital image is perfected using face detection in the acquired image is provided. Groups of pixels that correspond to plural images of faces are identified within a digitally acquired image, and corresponding image attributes to the group of pixels are determined. An analysis is performed of the corresponding attributes of the groups of pixels. It is then determined to activate the built-in flash unit based on the analysis. An intensity of the built-in flash unit is determined based on the analysis. Alternatively based on similar analysis, a digital simulation of the fill flash is performed on the image.

Within a digital acquisition device with a built in flash unit, the exposure of an acquired digital image is perfected using face detection in the acquired image is provided. Groups of pixels that correspond to plural images of faces are identified within a digitally acquired image, and corresponding image attributes to the group of pixels are determined. An analysis is performed of the corresponding attributes of the groups of pixels. It is then determined to activate the built-in flash unit based on the analysis. An intensity of the built-in flash unit is determined based on the analysis. Alternatively based on similar analysis, a digital simulation of the fill flash is performed on the image.

A method, system and program product for quantifying a risk of an expected unserved energy in an energy generation system using a digital simulation. An energy load demand forecast is generated based at least in part on a weather year model. A plurality of energy generation resources are committed to meet the energy load demand. An operating status is determined for each committed energy generation resource in the energy generation system. A determination is made as to whether or not the committed resources are sufficient to meet the energy load demand. A dispatch order for a plurality of additional energy resources is selected if the committed resources are not sufficient to meet the energy load demand. Additional resources are committed based on the selected dispatch order until the energy load demand is met. The expected unserved energy is determined and an equivalent amount of energy load demand is shed based at least in part on an expected duration of unserved energy and a customer class grouping. An associated cost for the expected unserved energy is also determined.

A method and system for fabricating a dental prosthesis are provided. High resolution digital scanned images of a patient's oral structures are acquired. Three dimensional (3D) cone beam X-ray images of hard and soft oral tissues are acquired. The scanned images are integrated with the 3D cone beam X-ray images in a 3D space to obtain combined three dimensional images of the oral structures. The occlusal relationship between upper and lower oral structures are digitally simulated using the combined three dimensional images. The dental prosthesis is digitally modeled for planning intra-oral positioning and structure of the dental prosthesis. The digital dental prosthesis model is refined based on simulated force tests performed for assessing interference and retention of the digital dental prosthesis model. A prospective dental prosthesis model is created based on the refined digital dental prosthesis model. The dental prosthesis is fabricated based on a verified prospective dental prosthesis model.

The invention discloses a transmitter and a transmitter signal processing method. The transmitter comprises a pre-distortion processing unit, a digital-analog conversion unit, a radio frequency unit, a power amplifier, a coupler, a feedback radio frequency unit, an analog-digital conversion unit, an adaptive tracking algorithm unit, a lookup table storage unit and a lookup table control unit; the lookup table control unit is used for detecting input digital baseband signals, and sending an update signal to the pre-distortion processing unit when a predestinated frame of input digital baseband signals ends; the pre-distortion processing unit takes a digital pre-distortion parameter out of the lookup table storage unit according to the update signal, and carries out pre-distortion on the input digital baseband signal according to the taken out digital pre-distortion parameter. The transmitter and the transmitter signal processing method ensure that signals output by the pre-distortion processing unit can not generate jumps, thus improving the pre-distortion effect of the input digital baseband signal, namely stability and reliability.

The invention discloses a field programmable gate array (FPGA)-based integrated circuit testing system, and a method for testing a digital-analog hybrid integrated circuit chip provided with a digital module or using a digital module as a main module and provided with a few analog modules by using the testing system. The system mainly comprises a personal computer (PC) machine, a main control chip, a FPGA chip, configuration information storage equipment and testing vector storage equipment. The testing method is implemented by the following steps that: the main control chip configures the FPGA chip, the main control chip sends a testing command to the FPGA chip, the FPGA chip sends an excitation signal to a chip to be tested and acquires the output response of the chip to be tested, or the analog parameter module acquires analog output response, the FPGA chip compares the output response or the analog output response of the chip to be tested with the testing information and judges the consistency of the output response and the testing information, and the chip to be tested is an accepted product or a defective product is judged. The system and the method can be widely applied in the field of integrated circuit chip test.

A highly integrated terrestrial and cable tuner for receiving digital and analog television signals is disclosed. It achieves high performances in sensitivity, image rejection, dynamic range, channel selectivity and power consumption. A major-images rejection converter disclosed rejects third- and fifth-order images. Thus it significantly relaxes RF filter design in a tuner of a single-stage or a first-stage zero-IF / low-IF downconversion architecture. Different architectures and frequency planning are disclosed in accordance with specifications of TV standards to improve the overall performance of the tuner with a different or configurable IF output. The tuner is integrated by using standard processes, with minimal off-chip components excluding SAW and LC filters. Small tuner modules cost less than discrete (can) tuners. They can be used in digital / analog TV sets and portable and handheld TV devices and for mobile-phone TV reception.

A data driving circuit for driving pixels of a display to display images with uniform brightness may include a gamma voltage unit that generates gray scale voltages, a digital-analog converter that selects, as a data signal, one of the gray scale voltages using first data, a decoder that generates second data using the first data, a latch for storing the first data and the second data, a current sink that receives a predetermined current from the pixel during a first partial period of a complete period for driving the pixel based on the selected gray scale voltage, a voltage controller that controls a voltage value of the data signal using the second data and a compensation voltage generated based on the predetermined current, and a switching unit that supplies the data signal to the pixel during any partial period of the complete period elapsing after the first partial period.

An audio reproduction system is divided into a central wave-field synthesis module and a plurality of loudspeaker modules disposed in a distributed way, wherein synthesis signals for the individual loudspeakers as well as corresponding channel information associated to the synthesis signals are calculated in the central wave-field synthesis module. The synthesis signals for a loudspeaker as well as associated channel information will then be transmitted to respective loudspeaker modules via a transmission path, wherein every loudspeaker module obtains the synthesis signals and associated channel information intended for the loudspeaker associated to the loudspeaker module. A distributed audio rendering and digital / analog converting takes place in the loudspeaker module to generate the actually analog loudspeaker signals in a distributed way in spatial proximity to every loudspeaker. The division into a central wave-field synthesis module and the plurality of distributed loudspeaker modules allows that audio reproduction systems that are scalable with regard to the price can be generated in order to offer systems of different size scalable in price particularly for cinema reproduction rooms varying strongly in size.

Structures and methods for fabricating high speed digital, analog, and combined digital / analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and / or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Methods and systems for a hybrid optical device for high dynamic range high resolution remote sensing of object distance, object motion displacement, object three dimensional structure, object spatial profile, and measurement of liquid levels, and different matter interface positions. The device uses a hybrid digital-analog controlled variable focal length lens system to target both specular and diffuse objects. The spatial processing methods and systems can include time-frequency processing optical distance measurement methods to enable a robust hybrid-technique sensor.

A device for the generation of analog signals by means of analog-digital converters comprises a block for the generation of words encoded on N bits and an analog-digital converter whose input is encoded on M bits, M being smaller than N. The device furthermore comprises a sigma-delta modulator, at the output of the first block, the bus being separated into M most significant bits reserved for the input of the analog-digital converter and N-M least significant bits that enter the sigma-delta modulator, the output of this modulator being an M-bit bus that is added to the M output bits of the word generation block by digital addition means, M being smaller than N.

A laptop device includes a personal computer, a cellular transceiver, a speakerphone, and a hybrid communications control unit. The device has connectors for attaching a headset, cellular control unit, land telephone line, and additional speakers and microphones. The micro-processor-controlled hybrid communications control unit includes a modem, a data access arrangement, and a tone generator as well as digital, analog, and power switches. The hybrid communications control unit switches the communications components and provides, under program control, the proper protocols, level, and impedance matching to connect the modem, speakerphone, headset, speaker / microphone, or cellular control unit to the landline or to the cellular network via the transceiver. Matching and switching operations are automatic and transparent to the user. The unit can also connect two of the terminal devices or connect the cellular and landlines for call relaying. The device is capable of connecting plural calls at the same time. The hybrid communications control unit may be controlled by its internal firmware, by toggle switches, or by commands issued from the personal computer.

A data driving circuit capable of displaying images having uniform brightness. The present invention provides a data driving circuit of a display device having: at least one current sinking unit for controlling a predetermined current to flow in a data line; at least one voltage generating unit for resetting voltage values of enhancement voltages using a compensation voltage generated when the predetermined current flows; at least one digital-analog converter for selecting as a data signal one of the enhancement voltages to correspond to a digital value of externally supplied data; at least one boosting unit for boosting a voltage value of the data signal; and at least one switching unit for providing the data line with the boosted data signal.

Systems and methods for asynchronous multi-channel data communications are provided. An embodiment of the invention includes a minimum of three channels for digital computation in Primary Flight Computers and four channels for digital / analog conversion in Actuation Control Electronics. Each channel (Primary Flight Computer or Actuation Control Electronics) contains two computation lanes with dissimilar processors and compilers. Hence with dual-dissimilar processors the computer architecture is fail-passive to generic errors. The two Actuation Control Electronics computation lanes select the digital control data of one of the two computation lanes of one of the three digital computation channels for conversion and transmission to associated actuators.

In a mobile terminal device having a processing unit and a memory unit, an acoustic echo cancellation and a microphone beamforming are provided. Said device includes a plurality of a microphones, a pre-processing stage has an amplifier and a signal converter for an analog-to-digital conversion. In a main signal processing stage, a pre-filter suitable for polynomial beamforming, an acoustic echo cancellation stage and a post-filter for polynomial beamforming are provided. Furthermore, a post-processing stage has an amplifier and a signal converter for a digital-to-analog conversion, and plurality of speakers.

The invention relates to a programmable multi-axis controller based on an IEEE-1394 serial bus in the technical field of numerical control. The programmable multi-axis controller comprises an IEEE-1394 serial communication interface module, a DSP module, an FPGA module, a differential motion reception module, a DA and operation amplification module, a photoelectric isolation module, a power supply and clock module and an auxiliary module, wherein the DSP module receives motion control information transmitted from the IEEE-1394 serial communication interface module and transmits a generated multi-axis motor pulse instruction to the FPGA module; and the FPGA module outputs the multi-axis motor pulse instruction to the DA and operation amplification module after the storage and frequency division treatment of the instruction so as to complete digital-analog conversion and operation amplification treatment and further control the operation of a multi-axis motor. The programmable multi-axis controller reduces the number of controller elements and the volume of an integrated circuit card, improves the flexibility and the expansibility of a system, and meets the requirements of the multi-axis real-time, high-speed and high-accuracy control in the technical field of numerical control.

A data driving circuit for a light emitting display may include a gamma voltage generator that generates gradation voltages, a current sink that receives a predetermined current from a pixel via a data line during a first partial period of one complete period for driving the pixel, a voltage generator that generates an incrementally increasing compare voltage during the first partial period, a comparator that compares a compensation voltage generated based on the predetermined current with the compare voltage and generates a logic signal based on a result of the compare, an adjusting unit that generates compensation data based on the logic signal, and a digital-analog converter that generates a composite data using the compensation data and externally supplied data and selects, as a data signal for the pixel, one of the plurality of gradation voltages based on a bit value of the composite data.

The invention discloses a battery management system with an active equalization system. The battery management system comprises a single chip microcomputer control circuit, the active equalization system and a data acquisition system, wherein the active equalization system and the data acquisition system are respectively connected with the single chip microcomputer control circuit; the active equalization system comprises a relay gating switch, an additional charge unit, an additional discharge unit and a digital analog switch; the data acquisition system comprises a battery cell voltage acquisition unit; the battery cell voltage acquisition unit comprises an integrated operational amplifier unit and a digital analog switch. According to the battery management system disclosed by the invention, the equalization system is provided with the additional charge unit and the additional discharge unit, and therefore equalization management can be performed on the voltage of each battery cell in a battery pack, and the phenomenon that the battery cells in the battery pack are overcharged or over-discharged can be further avoided; the battery management system disclosed by the invention can be widely applied in the aspects of communication, electric power, traffic and new energy, and has important significance in maintaining the normal operation of the battery pack.

Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

An object is to reduce power consumption of an analog-digital converter circuit. An analog potential obtained in a sensor or the like is held in a sample-and-hold circuit including a transistor with an extremely low off-state current. In the sample-and-hold circuit, the analog potential is held in a node which is able to hold a charge by turning off the transistor. Then, power supply to a buffer circuit or the like included in the sample-and-hold circuit is stopped to reduce power consumption. In a structure where a potential is held in each node, power consumption can be further reduced when a transistor with an extremely low off-state current is connected to a node holding a potential of a comparator, a successive approximation register, a digital-analog converter circuit, or the like, and power supply to these circuits is stopped.

An improved spread spectrum communication system includes a transmitter and a receiver utilizing a pilot channel for the transmission of pure rather than modulated PN codes for code acquisition or tracking purposes with a lower bit error rate. The pilot signal is used to obtain initial system synchronization and phase tracking of the transmitted spread spectrum signal. At the transmitter side, a Walsh code generator, a Walsh modulator, a first PN code generator, a first band spreader, a second band spreader, finite impulse response filters, digital-analog converters, low-pass filters, an intermediate frequency mixer, a carrier mixer, a band-pass filter are used to transmit a spread spectrum signal. At the receiver side, a corresponding band-pass filter, a carrier mixer, an intermediate-frequency mixer, low-pass filters, analog-digital converters, a second PN code generator, an I channel despreader, a Q channel despreader, a PN code synchronization controller, a Walsh code generator, a first Walsh demodulator, a second Walsh demodulator, accumulator & dump circuits, a combiner, and a data decider are used to demodulate a received spread spectrum signal

The invention relates to non-photorealistic rendering in computer graphics, in particular to digital simulation and synthesis with artistic style of Yunnan heavy-color painting, and belongs to the technical field of non-photorealistic graphic rendering. The digital simulation and synthesis are characterized in that: the digital simulation and synthesis comprise an establishment and management module of a Yunnan heavy-color painting basic graphic element library, a graphic element library-based Yunnan heavy-color painting traditional delineation drawing rendering module, and a Yunnan heavy-color painting traditional delineation drawing-based coloring and rendering module. The basic graphic element library is used for providing graphic elements needed by foreground traditional delineation drawings, such as hair, facial forms, trunks and the like. The Yunnan heavy-color painting traditional delineation drawing rendering module can select appropriate graphic elements from the graphic element library to combine the graphic elements by layers so as to generate the Yunnan heavy-color painting traditional delineation drawings. In order to harmoniously collocate all the graphic elements, a system provides multiple kinds of operation for the graphic elements, such as translation, selection, scaling and the like and can modify the shapes of the graphic elements at the same time. The Yunnan heavy-color painting traditional delineation drawing-based coloring and rendering module is in charge of coloring the traditional delineation drawings, and the effects of coloring can reflect texture characteristics and color characteristics in an original drawing of the heavy-color painting, and special characteristic simulation of the Yunnan heavy-color painting, such as character edge hollow sense, background fusion and the like is realized.

The present invention belongs to a technical field of an integrated circuit, and particularly to a low power consumption production line analog-digital converter which adopts an operational amplifier sharing. The analog-digital converter is composed of an input sampling holding circuit, a six-stage allowance gain circuit, an one-stage double-digit all-parallel analog-digital converter, a converting switch which is used for operational amplifier sharing, six sub-analog-digital converters, six sub-digital-analog converters, a production line output clock synchronous circuit and a digital correcting circuit. The sampling holding circuit and the six-stage allowance gain circuit are connected in sequence. The last stage is a double-digit all-parallel analog-digital converter. The input end of each stage of allowance gain circuit is connected with each stage of sub-analog-digital converter. Two continuous stages shares one operational amplifier. After the output clock synchronous circuit, the data with 14 digits is obtained, and after the digital correction of the digital correcting circuit, the final eight digit quantized output is obtained. The analog-digital converter realizes high speed and low power consumption.

The invention provides a successive approximation register analog-digital converter which comprises a digital-analog conversion unit, a comparison unit, a successive approximation logic control unit, a shift register and decoding unit and a clock generation unit. The successive approximation register analog-digital converter also comprises a signal feedback unit. An input terminal of the signal feedback unit connects with an output terminal of the comparison unit. An output terminal of the signal feedback unit connects with an input terminal of the successive approximation logic control unit. The signal feedback unit receives a comparison result outputted by the comparison unit, generates a feedback signal, outputs the feedback signal to the successive approximation logic control unit to trigger the successive approximation logic control unit to control the shift register and decoding unit to carry out shift motion, a problem that a whole analog-digital converter has a segment of idle time after a traditional successive approximation analog-digital converter compares unit latch difference signals is avoided, and a work speed of the successive approximation analog-digital converter is effective raised.

A voltage reference source with high-order temperature compensation circuit belongs to the electronic technical field. The voltage reference source comprises a starting current and positive temperature coefficient current generating circuit, a negative temperature coefficient current generating circuit, a high-order temperature compensation current generating circuit and a superimposition and summation output circuit. The added high-order temperature compensation current generating circuit performs linearization to the breakover voltage VBE between the voltage of the base and emitter of a triode to obtain a high-order compensation amount which is in agreement with the high-order temperature amount of the PN junction voltage, and the high-order temperature coefficient of the PN junction voltage can be eliminated fundamentally after proportional offset, thus realizing a CMOS voltage reference source with the lower temperature coefficient. The voltage reference source is prepared by the common CMOS technology with lower cost, has extremely low temperature coefficient, less power consumption and smaller area, and can be used in the reference circuits such as analog circuits and digital-analog hybrid circuits which are required to have low temperature coefficients.

The invention provides a method for analyzing the machining precision reliability sensitivity of a numerically-controlled machine tool, belongs to the field of machine tool precision design, and particularly relates to a space error modeling method of a three-axis machine tool and a method for analyzing the machining precision reliability and the machining precision reliability sensitivity of the machine tool. A multi-body system motion feature analysis method is used for setting up a space error model of the machine tool, and combined with a Monte-carlo digital analogy method for analyzing the machining precision reliability of the machine tool, and the degree of influence on the machining precision reliability from the wave action of all items of geometric errors of the machine tool, so that the critical geometric errors influencing the machining precision reliability are identified. Guiding advice can be given for designing, assembling and machining of the machine tool, and the machining precision reliability of the machine tool is improved fundamentally.