38 results about "Cmos electronics" patented technology

Structures and methods for fabricating high speed digital, analog, and combined digital / analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and / or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

Methods and systems for a photonic interposer are disclosed and may include receiving one or more continuous wave (CW) optical signals in a silicon photonic interposer from an optical source external to the silicon photonic interposer. The received CW optical signals may be processed based on electrical signals received from a CMOS electronics die bonded to the interposer, and modulated optical signals may be received in the interposer via optical couplers on the interposer. Electrical signals may be generated in the interposer based on the received modulated optical signals, and may be communicated to the CMOS electronics die. The generated electrical signals to may be communicated to the CMOS electronics die via copper pillars. The CW optical signals may be received in the interposer from an optical source assembly coupled to the interposer. The CW optical signals may be received from optical fibers coupled to the interposer.

A method of fabricating a composite semiconductor structure includes providing an SOI substrate including a plurality of silicon-based devices, providing a compound semiconductor substrate including a plurality of photonic devices, and dicing the compound semiconductor substrate to provide a plurality of photonic dies. Each die includes one or more of the plurality of photonics devices. The method also includes providing an assembly substrate having a base layer and a device layer including a plurality of CMOS devices, mounting the plurality of photonic dies on predetermined portions of the assembly substrate, and aligning the SOI substrate and the assembly substrate. The method further includes joining the SOI substrate and the assembly substrate to form a composite substrate structure and removing at least the base layer of the assembly substrate from the composite substrate structure.

Quantitative understanding of neural and biological activity at a sub-millimeter scale requires an integrated probe platform that combines biomarker sensors together with electrical stimulus / recording sites. Optically addressed biomarker sensors within such an integrated probe platform allows remote interrogation from the activity being measured. Monolithic or hybrid integrated silicon probe platforms would beneficially allow for accurate control of neural prosthetics, brain machine interfaces, etc as well as helping with complex brain diseases and disorders. According to the invention a silicon probe platform is provided employing ultra-thin silicon in conjunction with optical waveguides, optoelectronic interfaces, porous filter elements, and integrated CMOS circuitry. Such probes allowing simultaneously analysis of both neural electrical activities along with chemical activity derived from multiple biomolecular sensors with porous membrane filters. Such porous silicon and polymer filters providing biomolecular filtering and optical filtering being compatible with post-processing wafers with integrated CMOS electronics.

A radio frequency (RF) micro-electro-mechanical systems (MEMS) switch and high yield manufacturing method. The switch can be fabricated with very high yield despite the high variability of the manufacturing process parameters. The switch is fabricated with monocrystalline material, e.g., silicon, as the moving portion. The switch fabrication process is compatible with CMOS electronics fabricated on Silicon-on-Insulator (SOI) substrates. The switch comprises a movable portion having conductive portion selectively positioned with a bias voltage to conductively bridge a gap in a signal line.

Microelectromechanical systems (MEMS) are small integrated devices or systems that combine electrical and mechanical components. It would be beneficial for such MEMS devices to be integrated with silicon CMOS electronics and packaged in controlled environments and support industry standard mounting interconnections such as solder bump through the provisioning of through-wafer via-based electrical interconnections. However, the fragile nature of the MEMS devices, the requirement for vacuum, hermetic sealing, and stresses placed on metallization membranes are not present in packaging conventional CMOS electronics. Accordingly there is provided a means of reinforcing the through-wafer vias for such integrated MEMS-CMOS circuits by in filling a predetermined portion of the through-wafer electrical vias with low temperature deposited ceramic materials which are deposited at temperatures below 350° C., and potentially to below 250° C., thereby allowing the re-inforcing ceramic to be deposited after fabrication of the CMOS electronics.

An efficient deposition process is provided for fabricating reliable RF MEMS capacitive switches with multilayer ultrananocrystalline (UNCD) films for more rapid recovery, charging and discharging that is effective for more than a billion cycles of operation. Significantly, the deposition process is compatible for integration with CMOS electronics and thereby can provide monolithically integrated RF MEMS capacitive switches for use with CMOS electronic devices, such as for insertion into phase array antennas for radars and other RF communication systems.

A method of providing microelectromechanical structures (MEMS) that are compatible with silicon CMOS electronics is provided. The method provides for processing and manufacturing is steps limiting a maximum exposure of an integrated circuit upon which the MEMS is manufactured during MEMS manufacturing to below a temperature wherein CMOS circuitry is adversely affected, for example below 400° C., and sometimes to below 300° C. or 250° C., thereby allowing direct manufacturing of the MEMS devices onto electronic integrated circuits, such as Si CMOS circuits.

Group III nitride layers have a wide range of uses in electronics and optoelectronics. Such layers are generally grown on substrates such as sapphire, SiC and recently Si(111). For the purpose inter alia of integration with Si-CMOS electronics, growth on Si(001) is indicated, which is possible only with difficulty because of the different symmetries and is currently limited solely to misoriented Si(001) substrates, which restricts the range of use. In addition, the layer quality is not at present equal to that produced on Si(111) material. Growth on exactly oriented Si(001) and an improvement in material quality can now be simply achieved by a modification of the surface structure possible with a plurality of methods.

Capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics are disclosed. A capacitive based sensor is disposed over a first predetermined portion of a wafer that includes at least a first ceramic element providing protection for the final capacitive based sensor and self-aligned processing during its manufacturing.

MEMS based sensors, particularly capacitive sensors, potentially can address critical considerations for users including accuracy, repeatability, long-term stability, ease of calibration, resistance to chemical and physical contaminants, size, packaging, and cost effectiveness. Accordingly, it would be beneficial to exploit MEMS processes that allow for manufacturability and integration of resonator elements into cavities within the MEMS sensor that are at low pressure allowing high quality factor resonators and absolute pressure sensors to be implemented. Embodiments of the invention provide capacitive sensors and MEMS elements that can be implemented directly above silicon CMOS electronics.