788 results about "Analogue circuits" patented technology

A system and method that does trustworthy multi-objective structural synthesis of analog circuits, and extracts expert analog circuit knowledge from the resulting tradeoffs. The system defines a space of thousands of possible topologies via a hierarchically organized combination of designer-trusted analog building blocks, the resulting topologies are guaranteed trustworthy. The system can perform a search based on a multi-objective evolutionary algorithm that uses an age-layered population structure to balance exploration vs. exploitation, with operators that make the search space a hybrid between vector-based and tree-based representations. A scheme employing average ranking on Pareto fronts is used to handle a high number of objectives. Good initial topology sizings are quickly generated via multi-gate constraint satisfaction. To explicitly capture expert analog design knowledge, data mining is employed on the sized circuits to: automatically generate a decision tree for navigating from performance specifications to topology choice, to do global nonlinear sensitivity analysis, and to generate analytical models of performance tradeoffs.

The invention discloses an emergency call method, which particularly includes that: user equipment (UE) can send an emergency attachment request to an SAE network in evolution network; the emergency attachment request includes an emergency indication; the SAE network receives the emergency indication, and then selects an emergency call service entity for the UE; the UE can send out an emergency call request to the emergency call service entity after being emergently attached onto the SAE network; the emergency call service entity can establish the emergency voice carrying; and the UE can execute the emergency call according to the established emergency voice carrying. The embodiment of the invention provides the method which can finish the emergency call of the analogue circuit area with the help of the emergency call service entity in the evolution network, so as to realize the emergence call service in the SAE / LTE packet networks.

Structures and methods for fabricating high speed digital, analog, and combined digital / analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and / or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

A computational system can include digital circuitry and analog circuitry, for instance a digital processor and a quantum processor. The quantum processor can operate as a sample generator providing samples. Samples can be employed by the digital processing in implementing various machine learning techniques. For example, the computational system can perform unsupervised learning over an input space, for example via a discrete variational auto-encoder, and attempting to maximize the log-likelihood of an observed dataset. Maximizing the log-likelihood of the observed dataset can include generating a hierarchical approximating posterior. Unsupervised learning can include generating samples of a prior distribution using the quantum processor. Generating samples using the quantum processor can include forming chains of qubits and representing discrete variables by chains.

A smart controller chip for controlling an active matrix display. Within the controller chip, circuitry for generating analog reference levels is incorporated alongside circuitry for generating digital timing and control signals. The combination of D / A analog circuitry and standard digital logic makes the controller uniquely suited for addressing all the panel control needs both for the normal digital functions but also for control of the analog aspects of the panel, like display gamma. The analog reference levels and the digital signals are made programmable using registers internal to the controller chip. The contents of these registers are programmed initially by digital values stored in an external PROM or in flash memory integrated into the controller chip. In addition, software in a host system is able to program these registers via an interface between the host system and the controller chip.

A method for diagnosing analog circuit fault based on vector-valued regularized kernel function approximation, includes steps of: step (1) acquiring a fault response voltage signal of an analog circuit; step (2) carrying out wavelet packet transform on the collected signal, and calculating a wavelet packet coefficient energy value as a characteristic parameter; step (3) utilizing a quantum particle swarm optimization algorithm to optimize a regularization parameter and kernel parameter of vector-valued regularized kernel function approximation, and training a fault diagnosis model; and step (4) utilizing the trained diagnosis model to recognize circuit faults.

A novel analog circuit early fault diagnosis method includes the steps of (1) acquiring time domain response signals of an analog circuit and taking the time domain response signals as output voltage signals of the analog circuit; (2) performing wavelet transform to the acquired voltage signals; (3) performing fractal analysis to original signal patterns and wavelet sub patterns to generate wavelet fractal dimensions of different patterns; (4) performing kernel entropy component analysis to candidate feature vector data composed of the wavelet fractal dimensions to acquire low-dimension feature vector data; (5) creating a multi-class classifier of a least squares support vector machine, and optimally selecting penalty factor and width factor of the least squares support vector machine, which are used for distinguishing overlapped early fault categories, by a quantum-behaved particle swarm optimization algorithm; and (6) sending the low-dimension feature vector data into the multi-class classifier of the least squares support vector machine and then outputting early fault diagnosis results. The novel analog circuit early fault diagnosis method can effectively detect early faults of analog circuits.

An output circuit, a digital / analog conversion circuit and a display apparatus can reduce the number of required input voltages and the number of transistors to save the necessary area. The output circuit and the digital / analog conversion circuit comprise a selection circuit for receiving as input a plurality of (m) reference voltages having mutually different respective voltage values, selecting two of the voltages according to a selection signal and outputting them and an amplifier circuit for receiving as input the voltages output from the selection circuit at two input terminals T1, T2 and outputting the voltage obtained by interpolating the voltage difference of the two input terminal voltages V(T1), V(T2) to a predetermined ratio. It may alternatively be so arranged that the selection circuit sequentially outputs the selected two voltages and the amplifier circuit sequentially receives as two input the two voltages and outputs the output voltage obtained by interpolation.

The invention relates to the field of strand displacement, and provides a color image encryption method based on a DNA strand displacement analog circuit. Firstly, a reaction module with a light-emitting group and a quenching group is designed through Visual DSD software, and by utilizing the equivalence of a DNA strand displacement reaction module and an ideal reaction module, an analog circuit formed by the DNA strand displacement reaction module can perform analog on the dynamics characteristics of an ideal reaction network formed by the ideal reaction module, wherein the Rössler chaotic system can be described by the idealized reaction network. Secondly, data generated by the DNA strand displacement analog circuit is converted into a chaotic sequence matched with a plaintext image in size after being extended, and finally, the color image encryption effect is achieved through scrambling and diffusion operations.

A display device includes an inaction control circuit and a DCK-PLL circuit. The inaction control circuit stops driving of driving circuits, such as a signal line driving circuit, a scanning line driving circuit, analog circuit and the like, which are provided for driving an active matrix panel. The inaction control circuit stops the control circuits in a non-refresh period where all scanning lines become non-scanning state and provided between refresh periods for scanning a screen of the active matrix panel. The inaction control circuit also stops driving of the DCK-PLL circuit in the non-refresh period, in addition to stopping driving of the driving circuits.

The invention provides a temperature sensor applied to a metering ammeter. The temperature sensor comprises an analog circuit portion, a digital circuit portion and a user ARM portion. The analog circuit portion comprises a positive temperature coefficient current generator in direct-proportion current bias with an absolute temperature, a bias current mirror array, a low-temperature drift coefficient reference current source, a temperature-sensitive transistor and an analog-to-digital conversion integrator. The digital circuit portion comprises a switch control logic, a digital code output, a digital counter and a shift register. The analog-to-digital conversion integrator has a sampling capacitor and an integrating capacitor, of which the capacitance is same; and bias current of the temperature-sensitive transistor is biased by six unit current mirrors in turns in a proportion of 5:1. According to a temperature trimming method for the temperature sensor, the number of the bias current mirrors is 6, wherein 5 paths of currents are used for coarse tuning, and the other one path of current is used for fine tuning; when the output bias of the counter is relatively large, the 5 paths of coarse-tuning currents are used; and when the output of the counter is between the two paths of unit currents, fine tuning is used.

The invention provides a low-dropout linear regulator circuit with a high power supply rejection ratio, and belongs to the field of analog circuit integration. The low-dropout linear regulator circuitcomprises a bias module, an error amplifier, a buffer and an output stage, wherein the bias module provides bias voltage; a positive input end of the error amplifier is connected to reference voltage, a negative input end of the error amplifier is connected to feedback voltage, and an output end of the error amplifier passes through the buffer and the output stage to be connected to an output endof an LDO; the buffer comprises an amplification stage, a high-pass filter and a current source, and the amplification stage is connected between an input end and output end of the buffer; the current source is connected between power supply voltage and the output end of the buffer; the high-pass filter comprises a first NMOS transistor, a first PMOS transistor, a second PMOS transistor and a first capacitor, a grid electrode of the first PMOS transistor is connected with the bias voltage, a source electrode of the first PMOS transistor is connected with power supply voltage and is connectedto a drain electrode of the first PMOS transistor, a grid electrode of the second PMOS transistor and a grid electrode and drain electrode of the first NMOS transistor after passing through the firstcapacitor; a source electrode of the second PMOS transistor is connected with the output end of the buffer, and a drain electrode of the second PMOS transistor is connected with a source electrode ofthe first NMOS transistor and is grounded. The low-dropout linear regulator circuit with the high power supply rejection ratio improves the power supply rejection ratio.

The present invention relates amplifiers using metal oxide semiconductor based integrated circuits. The present invention is particularly but not exclusively related to audio application mixed signal chips. The present invention provides an analogue circuit for processing analogue signals in an integrated circuit comprising a number of metal oxide semiconductor transistor devices, the circuit stage comprising a first said transistor device having a first oxide thickness, and a second said transistor device having a second and different oxide thickness. Preferably a cascode based op amp structure is implemented.

A built-in-self test (BIST) scheme for analog circuitry functionality tests such as frequency response, gain, cut-off frequency, signal-to-noise ratio, and linearity measurement. The BIST scheme utilizes a built-in direct digital synthesizer (DDS) as the test pattern generator that can generate various test waveforms such as chirp, ramp, step frequency, two-tone frequencies, sweep frequencies, MSK, phase modulation, amplitude modulation, QAM and other hybrid modulations. The BIST scheme utilizes a multiplier followed by an accumulator as the output response analyzer (ORA). The multiplier extracts the spectrum information at the desired frequency without using Fast Fourier Transform (FFT) and the accumulator picks up the DC component by averaging the multiplier output.

Provided is a method of fabricating a silicon germanium (SiGe) Bi-CMOS device. In the fabrication method, the source and drain of the CMOS device is formed using a silicon germanium (SiGe) heterojunction, instead of silicon, thereby preventing a leakage current resulting from a parasitic bipolar operation. Further, since the source and drain is connected with an external interconnection through the nickel (Ni) silicide layer, the contact resistance is reduced, thereby preventing loss of a necessary voltage for a device operation and accordingly, making it possible to enable a low voltage and low power operation and securing a broad operation region even in a low voltage operation of an analogue circuit.

An analog implementation is proposed of an adaptive signal processing model of a kind requiring a plurality of randomly-set variables. In particular, following a digital to analog conversion of a digital input signal, analog processing is used to transform the data input to the model into data which is subsequently processed by an adaptively-created layer of the model. In the analog processing, multiplication operations involving the randomly-set variables are performed by analog circuitry in which the randomly-set variables are the consequence of inherent tolerances in electrical components. This eliminates the need for the randomly-set variables to be implemented in some other way, for example as random variables stored in memory.

The invention discloses a chip design method for a multi-chip module of a high-performance processor with an optical interface so as to solve the problems of the hybrid integration of the optical interface pin based on an MT locating pin with the pin of ball grid array (BGA) of a high-speed electrical interface of the high-performance processor, and the hybrid integration of a high-speed digital circuit with an analog circuit. The invention has the technical scheme that a photoelectric conversion chip substrate and a microprocessor chip substrate PCB are firstly made; a photoelectric conversion bare chip and the photoelectric conversion chip substrate PCB are integrated after testing; then multiple chips are assembled; the microprocessor chip substrate PCB with the multiple chips is encapsulated, thus obtaining an MCM chip; and at last the MCM chip is tested. The invention solves the problem of the hybrid integration of optical and electrical pins, devices and circuits. A chip for the multi-chip module of a high-performance processor can be designed and has high electromagnetic interference resistance and favorable signal transmission characteristic.