293results about "Pulse generation by bipolar transistors" patented technology

Precision integrated time reference circuits are disclosed. Preferred embodiments provide time reference circuits that are relatively insensitive to variations in process, supply, and temperature. A preferred embodiment of the invention is disclosed in which a relaxation oscillator according to the invention includes a reference voltage circuit configured to maintain a reference voltage in proportion to actual circuit resistance values. Aspects of the invention also include dynamic compensation for variations in temperature.

A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

In a switching power supply device with reduced size and increased power conversion efficiency, a first resonant circuit including a series resonant inductor and a series resonant capacitor, and a second resonant circuit including a series resonant inductor and a series resonant capacitor, are caused to resonate with each other to cause sympathetic vibration of each resonant circuit, such that transmission is performed by utilizing both magnetic field coupling and electric field coupling between a primary winding and a secondary winding. Operation at a switching frequency higher than a specific resonant frequency of an overall multi-resonant circuit allows a ZVS operation to be performed, enabling a significant reduction in switching loss and high-efficiency operation.

Temperature-stabilized oscillator circuit A temperature-stabilized oscillator circuit (1) comprises a first part with a first temperature dependence and a second part with a second temperature dependence, which is different from the first temperature dependence. A charge storage device (C2), a controllable upward-integration current source (T2) for charging the charge storage device (C2), a controllable downward-integration current source (TB3) for discharging the charge storage device (C2) and two resistors (R2, R1) having the same temperature coefficients are contained in each case in one of the two parts.

A free running clock circuit includes a switching circuit for switching between first and second logic states at a predetermined frequency based upon a trip voltage the switching circuit has a programmable temperature profile associated therewith. The switching circuit includes a comparator circuit that has first and second comparators. The first and second comparators have a reference input connected to receive the trip voltage, and the output of the comparators change logic states between a first logic state and a second logic state when the other input of the comparator passes the trip voltage. The first and second comparators have a programmable offset voltage enabling programming of the programmable voltage supply profile of the switching circuit. An RC timing circuit defines when the outputs of the comparators switch between the first and second logic states by providing a feedback to the other inputs of the two comparators. A temperature compensated trip voltage generator outputs a defined trip voltage that is compensated over temperature to offset the temperature profile of said switching circuit to provide an overall temperature compensated operation for said free running clock circuit.

A switched-current oscillator having a dc current source adapted to charge a capacitor so that the capacitor charging time is controlled based on a sequence of (pseudo)randomly selected values, each of those values defining a corresponding charging time. A discharge device is adapted to discharge the capacitor if the voltage across the capacitor reaches a threshold voltage, at which point the next value in the sequence is selected to determine the next charging time. A square-wave clock signal having spread-spectrum characteristics is generated in the oscillator by using the series of charge-discharge cycles corresponding to the sequence of randomly selected values to toggle a flip-flop operating as a delay line and zero-order hold.

A relaxation oscillator for generating an oscillator output signal having a predetermined frequency. The relaxation oscillator includes an interleaved charge pump for providing a restoring charge to an integrator in response to at least one charge pump control signal. The relaxation oscillator further includes an integrator having an integrator input connected to the current summing node. The integrator is adapted to produce an integrator output signal having the predetermined frequency at an integrator output. A comparator having an input connected to the integrator output is adapted to generate the oscillator output signal having the predetermined frequency in response to the integrator output signal.

An RC oscillator integrated circuit includes: an active current mirror connected to an external resistor, for receiving a current signal corresponding to a voltage signal applied to the external resistor, performing 1 / N-times division of the received current signal according to an input clock signal, and generating a 1 / N-times current signal; an oscillation circuit for generating an output voltage corresponding to a charging- or discharging-operation of a capacitor via a current path formed by the active current mirror; a feedback switching circuit for controlling a charging- or discharging-path of the capacitor by a feedback of an output signal Vo of the oscillation circuit; and a divider for generating not only a first clock signal capable of driving the active current mirror according to the output signal of the oscillation circuit, but also a second output clock signal having a compensated mismatch of the active current mirror.

A frequency dithering circuit reduces emissions that cause Electro-Magnetic Interference (EMI) by spreading the spectrum of a clock. The clock sequences a counter that drives a digital count value to a digital-to-analog converter (DAC). The DAC outputs a sawtooth wave with a wide voltage swing. A subtractor scales down the voltage swing to produce a reduced-swing sawtooth wave which is used as an upper limit voltage. Comparators trigger a set-reset latch to toggle the clock when current pumps charge and discharge a capacitor beyond voltage limits. Since the upper limit voltage is the reduced sawtooth wave from the subtractor, the amount of time to charge the capacitor varies, dithering the period of the clock. The degree of dithering can be adjusted by programming the feedback resistance in the subtractor. The subtractor reduces the sensitivity of dithering to errors in the DAC, allowing for an inexpensive, less precise DAC.

A quadrature output high-frequency RF divide-by-two circuit includes a pair of differential complementary logic latches. The latches are interconnected to form a toggle flip-flop. Each latch includes a tracking cell and a locking cell. In a first embodiment, the locking cell includes two complementary logic inverters and two transmission gates. When the locking cell is locked, the two gates are enabled such that the locked (i.e., latched) signal passes through both transmission gates and both inverters. In one advantageous aspect, the tracking cell only involves two transmission gates. Due to the circuit topology, the first embodiment is operable from a low supply voltage at a high operating frequency while consuming a low amount of supply current. In a second and third embodiment, the tracking cell involves a pair of inverters. The sources of the transistors of the inverters are, however, coupled together thereby resulting in performance advantages over conventional circuits.

The present invention provides a pulse width modulation (PWM) circuit comprising an PWM control circuit for setting an output signal to low when a logical level of a oscillation signal at a first input terminal changes from low to high, for resetting the output level to low in response to an effective input signal at a second terminal, a charge and discharge means for charging a first node (node1) when the output stays in low, for discharging the stored charge of node1 when the output stays in high, a comparator (C1) for outputting an output signal to the second terminal according to the first node signal and a first reference signal (Vref0), a discharge current controlling means for the stored charge on the first node, wherein the discharge current controlling means comprises a bias circuit 2 for controlling the discharge current based on constant current.

A method for producing an oscillating signal comprises: generating an oscillating signal by discharging after charging to a high trigger level and charging after discharging to a low trigger level; and turbo-charging at the initial of a change-over from charging to discharging while resuming a normal charging / discharging thereafter, and vice versa. The present invention makes use of the turbo-charging / discharging for a linear compensation, such that the produced oscillating signal has the features of concurrently eliminating phase noises and jitters as well as maintaining the modulation linearity.