60results about How to "Reduce layout size" patented technology

A multi-antenna module comprises a ground plane, a primary conductor, a secondary conductor and a plurality of coupling conductors, wherein the framework of the parallel primary radiation arm and secondary radiation arm can infinitely expand the number of antenna units in the same antenna structure. The capacitive coupling effect of parallel radiation arms and the inductance of the radiation arms themselves can effectively reduce the signal interference between antennae, whereby a plurality of antennae can be integrated to achieve antenna miniaturization. The primary conductor, the secondary conductor and the coupling conductors are all connected to the same ground plane, whereby the layout space is reduced, and the multi-antenna module is easy-to-assemble for various electronic devices.

A multi-antenna module comprises a ground plane, a primary conductor, a secondary conductor and a plurality of coupling conductors, wherein the framework of the parallel primary radiation arm and secondary radiation arm can infinitely expand the number of antenna units in the same antenna structure. The capacitive coupling effect of parallel radiation arms and the inductance of the radiation arms themselves can effectively reduce the signal interference between antennae, whereby a plurality of antennae can be integrated to achieve antenna miniaturization. The primary conductor, the secondary conductor and the coupling conductors are all connected to the same ground plane, whereby the layout space is reduced, and the multi-antenna module is easy-to-assemble for various electronic devices.

The invention discloses a floating fan base with flare type tension legs, a marine wind-driven generator and a construction method. The floating fan base comprises a top supporting platform, a bottom supporting structure, at least three hollow stand columns and a ballast regulating system, wherein the top supporting platform is used for supporting a pylon, blades and a wind-driven generator set; the bottom supporting structure is connected with multiple tension legs; the top supporting platform is connected with the bottom supporting structure via the hollow stand columns, the hollow stand columns are arranged around the vertical center line of the floating fan base, and each stand column inclines outwards from a lower end to an upper end relative to the vertical center line of the floating fan base; the ballast regulating system is arranged in the stand columns and / or the bottom supporting structure. The marine wind-driven generator of the base with the structure has excellent movement performance, integral wet towing can be performed, and the floating fan base and the marine wind-driven generator are convenient to manufacture, assemble and mount.

A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

The present invention provides a pulse width modulation (PWM) circuit comprising an PWM control circuit for setting an output signal to low when a logical level of a oscillation signal at a first input terminal changes from low to high, for resetting the output level to low in response to an effective input signal at a second terminal, a charge and discharge means for charging a first node (node1) when the output stays in low, for discharging the stored charge of node1 when the output stays in high, a comparator (C1) for outputting an output signal to the second terminal according to the first node signal and a first reference signal (Vref0), a discharge current controlling means for the stored charge on the first node, wherein the discharge current controlling means comprises a bias circuit 2 for controlling the discharge current based on constant current.

A circuit topology is configured to flatten out a phase- and amplitude-response over a specified range of frequencies. The circuit topology also provides a large cumulative phase-shift. In one embodiment, the circuit topology cascades a plurality of all-pass sections, with the center-frequencies of each all-pass section staggered to create a substantially flat phase-response over a frequency range. Further, in one embodiment the plurality of all-pass sections has at least one all-pass section that is different from another all-pass section. Each all-pass section includes a tunable capacitor and has a center-frequency that can be varied by electronically tuning the capacitor. Each center frequency is selected to obtain substantially constant amplitude and phase response over a desired frequency range and capacitance tuning range.

A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

A semiconductor ESD protection apparatus comprises a substrate; a first doped well disposed in the substrate and having a first conductivity; a first doped area having the first conductivity disposed in the first doped well; a second doped area having a second conductivity disposed in the first doped well; and an epitaxial layer disposed in the substrate, wherein the epitaxial layer has a third doped area with the first conductivity and a fourth doped area with the second conductivity separated from each other. Whereby a first bipolar junction transistor (BJT) equivalent circuit is formed between the first doped area, the first doped well and the third doped area; a second BJT equivalent circuit is formed between the second doped area, the first doped well and the fourth doped area; and the first BJT equivalent circuit and the second BJT equivalent circuit have different majority carriers.

A high density, low voltage, and low-power one time programmable (OTP) memory is based on core cells with a one transistor design. A CLEAN pulse is directed to a single shunt device at the output of the column decoder so spurious charges that may have been stored in the floating nodes can be cleaned up. Such arrangement also allows for the simultaneous initialization of bit lines, data lines, and sensing lines to zero. Core area layout size is substantially reduced, and operational power requirements are exceeding low making these particularly suitable in HF and UHF RFID applications.

A circuit topology is configured to flatten out a phase- and amplitude-response over a specified range of frequencies. The circuit topology also provides a large cumulative phase-shift. In one embodiment, the circuit topology cascades a plurality of all-pass sections, with the center-frequencies of each all-pass section staggered to create a substantially flat phase-response over a frequency range. Further, in one embodiment the plurality of all-pass sections has at least one all-pass section that is different from another all-pass section. Each all-pass section includes a tunable capacitor and has a center-frequency that can be varied by electronically tuning the capacitor. Each center frequency is selected to obtain substantially constant amplitude and phase response over a desired frequency range and capacitance tuning range.

In an RC calibration circuit, a single reference current is used to generate voltages across both a resistive and capacitive element. The component value of one of the resistive and capacitive element is successively altered until the voltages are substantially equal. Additionally, parasitic capacitances in the circuit are precharged to the resistive element voltage prior to the comparison. The RC calibration circuit eliminates the errors due to current matching and parasitic capacitances in prior art calibration circuits. The circuit includes a comparator and a digital control circuit (DCW) including a successive approximation register (SAR) holding the value of the digital control word used to control the component value of the tunable resistive or capacitive element. The SAR alters the DCW in an iterative, bit-by-bit binary searching pattern in response to the comparator output.

Reconfigurable units each include a hardware circuit having one part of a radio procedure function and a reconfigurable circuit having another part of the radio procedure function. An extension interface unit includes a switch circuit having a changeable connection specification to interconnect the reconfigurable units. A memory unit stores logic information for changing logics of the reconfigurable circuits and the connection specification of the switch circuit. A control unit downloads into the memory unit the logic information supplied from outside of the software defined radio. Rewriting the logics of the reconfigurable circuits according to the logic information and switching connection information of the switch circuit makes it possible to realize an optimum logic circuit in compliance with a radio communication to be used. In other words, it is possible to improve the scalability of the radio procedure function of the software defined radio.

A semiconductor memory device, having a 6F2 open bit line structure, connects each bit line of a bit line pair to a respective bit line of a neighboring bit line pair for a precharge operation so that a layout size of the semiconductor memory device decreases. Plural first precharge units each precharge one bit line of a first bit line pair and one bit line of a second bit line pair in response to a bit line equalizing signal. Plural sense amplifiers each sense a data bit supplied to a respective one of the first and second bit line pairs and amplify sensed data.

To provide a technique capable of achieving high integration of semiconductor devices. A standard cell is provided in an n-type well, and includes a p+-type diffusion layer and n+-type diffusion layer covered with a metal silicide film. The p+-type diffusion layer constitutes a source / drain of an MIS transistor, and the n+-type diffusion layer constitutes a tap. The p+-type diffusion layer is electrically coupled to a wiring layer via a contact, and the n+-type diffusion layer is electrically coupled to a wiring layer via a contact. Moreover, the p+-type diffusion layer is in contact with the n+-type diffusion layer. A power supply potential supplied to the source node of the MIS transistor is provided using two layers, i.e., the diffusion layer and the wiring layer.

Output stage and related method applied to source driver / chip of LCD panel. While performing dot polarization inversion for even / odd channels of LCD panel, n-channel and p-channel MOS transistors of symmetric layout are respectively adopted for alternately transmitting a positive polarization signal of higher swing range and a negative polarization signal of lower swing range from corresponding drivers of asymmetric layout to the even / odd channels, such that a layout area for alternating polarizations can be reduced. Also, the invention directly ties inputs of the output drivers to VDD or VSS so as to turn off the drivers for providing high impedance at the even / odd channels when necessary.

An imaging optical system includes three reflecting mirrors having first to third reflection surfaces and is configured, such that in an XYZ orthogonal coordinate system using an optical axis at the center of the field of view as Z-axis, the optical axis at the center of the field of view and an optical axis of an image plane are in parallel to each other by changing orientation of the optical axis in a YZ section while maintaining the orientation of the optical axis in an XZ section. At least one of the three reflection surfaces is rotationally asymmetric. Assuming that along the path of the beam traveling along the optical axis at the center of the field of view a distance between the second reflection surface and the third reflection surface is L2, a distance between the third reflection surface and the image plane is L3 and fy1 and an equivalent F-number of the imaging optical system is represented as Fno, the relational expression0.5<Fno(L2 / L3)<1.3is satisfied.

The invention provides a composite material substation structure. The composite material substation structure comprises herringbone columns, cross beams, ground wire columns, diagonal draw bars, wire hanging tube clamps, lightning rods, lightning conductors and crawling ladder assemblies, wherein ground wire column connectors are arranged on the tops of the herringbone columns, and cross beam connectors are arranged on the two sides of the herringbone columns; one ground wire column is mounted on the top of each herringbone column; one cross beam is connected between the two herringbone columns; the tops of the ground wire columns are connected with the wire hanging tube clamps in the middle parts of the cross beams through the diagonal draw bars; one or more cable-stayed structural gantry frames are formed; the wire hanging tube clamps mounted on the cross beams serve as wire hanging point connectors, the wire hanging tube clamps are made of rolled steel, aluminum alloy or a non-metallic composite material, and the herringbone columns, the cross beams, the ground wire columns, the diagonal draw bars and the crawling ladders are made of non-metallic composite materials; insulators are shortened through the structure, the height and width of the structure are reduced, and thus the floor area is reduced, and the lightning protection and earthquake prevention effects are improved; meanwhile, the land expropriation cost of an engineering project can be reduced, the reliability of safe operation is improved, and the resources are saved.

A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.

The semiconductor output circuit of the invention has an insulated gate transistor including a first terminal, a second terminal and a gate terminal, a conductive state of the insulated gate transistor being controlled by a drive circuit connected to the gate terminal, a capacitive element and a first resistor connected in series between the second terminal and the gate terminal, and a second resistor connected between the gate terminal and the first terminal. The insulated gate transistor has a cell area formed on a semiconductor substrate, in which a plurality of unit cells each defining a unit transistor connected between the first and second terminals are laid out. The second resistor has such a resistance that all of the unit transistors defined by the unit cells are turned on uniformly when electrostatic discharge is applied to the first or second terminal.

The invention discloses a solar energy coupling air source heat pump integrated domestic hot water system and a heating method thereof. A solar evaporation heat collector is arranged on inner surface of a shell of an outdoor unit of a solar energy air source heat pump, and an indoor automatic-controlled heat preservation water tank is arranged in a room and regulated and controlled by a control system through a circulation pipeline to achieve solar energy coupling air source heat pump integrated domestic hot water supplying. According to the solar energy coupling air source heat pump integrated domestic hot water system and the heating method thereof, functional advantage complementation of the solar energy and the air source heat pump is achieved by controlling the coupling system, and on the basis of momentarily and sufficiently supplying domestic hot water of which the temperature is intuitively and individually set to a user, the operation cost of the system is further lowered, and the function guarantee performance and using comfortableness of the system are improved.

Disclosed herein is a word line driving circuit in which sub-word lines are prevented from floating by using a sub-word line driver having two transistors. A plurality of sub-word line drivers is connected to one main word line. Each of the plurality of the sub-word lines includes a PMOS transistor and a NMOS transistor serially connected between a sub-word line driving voltage FX and a ground voltage. A floating prevention unit selects the main word line to a level of a threshold voltage using a driving signal having the level of the threshold voltage, thus preventing sub-word lines of a sub-word line driver, where the sub-word line driving voltage FX is off, from floating.

Output stage and related method applied to source driver / chip of LCD panel. While performing dot polarization inversion for even / odd channels of LCD panel, n-channel and p-channel MOS transistors of symmetric layout are respectively adopted for alternately transmitting a positive polarization signal of higher swing range and a negative polarization signal of lower swing range from corresponding drivers of asymmetric layout to the even / odd channels, such that a layout area for alternating polarizations can be reduced. Also, the invention directly ties inputs of the output drivers to VDD or VSS so as to turn off the drivers for providing high impedance at the even / odd channels when necessary.

A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.

A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out; a storage configured to store N-bit code values according to a plurality of detected phase differences; and a controller configured to share the N-bit code counter, control the generation of the N-bit code values according to the plurality of detected phase differences, and control the storing of the N-bit code values in an allocated space of the storage.

An electric transmission line tower made of composite materials is provided with a left assembly and a right assembly. The left assembly and the right assembly both comprise tower heads, cross arms, tower body upper sections and tower body lower sections. The electric transmission line tower is characterized in that the tower heads and the tower body upper sections are made of composite materials, the tower body lower sections are made of steel pipe poles or composite materials, the steel pipe poles of the tower body lower sections are connected with metal ladders or ladders made of composite materials, the tower body upper sections are connected with the ladders made of composite materials, the tower heads are connected with a single ladder made of composite materials, the left cross arms and the right cross arms are formed by parallel double poles, and two ends of the left cross arms and the right cross arms are connected with the top ends of the tower heads through double inclined draw bars. The tower made of composite materials is simple in structure, easy to assemble, long in service life and capable of resisting corrosion and aging and oxidation, eliminates suspension insulator strings on the existing towers, reduces electrical distance, reduces electrical distribution size, narrows line channels, is light in weight and free of maintenance, reduces line cost and saves operation cost.

The invention provides an organic waste gas recovery device and process, and belongs to the technical field of organic waste gas treatment. The device comprises a condensation system, a membrane separation system, an adsorption system and a vacuum system, the vacuum system comprises a first vacuum pump and a second vacuum pump which operate independently, an inlet and an outlet of the first vacuum pump are connected with the membrane separation system and the condensation system respectively, and organic gas separated from the membrane separation system is circulated back to the condensation system through the first vacuum pump; an inlet and an outlet of the second vacuum pump are respectively connected with the adsorption system and the condensation system; and desorbed organic gas in the adsorption system is circulated back to the condensation system through the second vacuum pump. According to the invention, the membrane separation system and the adsorption system respectively carry out organic gas and air separation and organic matter desorption through independent vacuum pumps, so that the two systems do not interfere with each other, the intermittent vacuum operation of the adsorption system does not influence the continuous vacuum operation of the membrane separation system, and the working stability of the membrane separation system is effectively guaranteed.

A 66kv side structure of a compact 500kv main transformer comprises an A, B, C three-phase transformer. The three-phase transformer is connected to a main loop through a triangle bus. The main loop is connected with a 66kv bus and a switch branch loop. The 66kv bus and the switch branch loop are connected with each branch loop. The branch loop comprises: a capacitance branch loop and a reactance branch loop. The capacitance branch loop comprises: a shunt capacitor group and a series reactor connected with the shunt capacitor group. The reactance branch loop comprises a three-phase reactor. The triangle bus uses a gas insulation bus to complete triangle winding. In the capacitance branch loop, A, B, C three phases are superposed to place in the each shunt capacitor group. In the reactance branch loop, the reactor is a superposition-type dry parallel hollow reactor or a magnetic-shielding parallel reactor.

The invention relates to a hydraulic station and provides a portable small and light high-power hydraulic station to solve the problem that for the need of high-power in narrow spaces and the like, an existing hydraulic station cannot be used. A heat pipe radiator of the portable small and light high-power hydraulic station is fixedly installed in an oil tank, one end of an oil tank oil return pipe is welded and fixed to the oil tank, the other end of the oil tank oil return pipe is connected with a low-pressure oil return valve connector, the oil outlet end of the oil tank is connected with an oil inlet of a hydraulic pump through a connector, the hydraulic pump is connected with an outer rotor motor, the oil outlet end of the hydraulic pump is connected with an integrated valve through a connector, an overflow valve, a filter, a pressure sensor and an energy storage device are installed on the integrated valve, one end of a valve oil return pipeline is connected with the integrated valve through a connector, the other end of the valve oil return pipeline is connected with a low-pressure oil return valve through a connector, one end of a high-pressure oil pipeline is connected with the integrated valve through a connector, the other end of the high-pressure oil pipeline is connected with a high-pressure oil outlet valve through a connector, an electronic speed controller device is arranged above the high-pressure oil pipeline, and a hydraulic assembly is arranged in a hydraulic assembly shell. The portable small and light high-power hydraulic station is used for meeting the need of high power in narrow spaces and the like.