4042 results about "Diffusion layer" patented technology

A high-density N-type diffusion layer 116 formed in a separation area 115 makes it possible to reduce a collector current flowing through a parasitic NPN transistor 102. Thus, a normal CMOS process can be used to provide a driving circuit and a data line driver which make it possible to improve resistance to possible noise occurring between adjacent terminals, while controlling a chip size.

A semiconductor memory device according to the present invention includes: a plurality of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells arranged in an array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and a plurality of dummy transistors 32-j each of which is formed between two adjacent ones of the plurality of N-ch MOS transistors 30-k so as to share diffusion layers with adjacent N-ch MOS transistors 30 and each of which has a gate electrode supplied with a voltage for electrically insulating these adjacent transistors 30-k.

A method for manufacturing a semiconductor substrate comprises the steps of: forming a gate oxide film as an insulating layer on the surface of a semiconductor substrate; implanting boron ions for inhibiting the migration of a peeling substance in the semiconductor substrate to form an anti-diffusion layer in the semiconductor substrate; activating boron in the anti-diffusion layer by heat treatment; implanting hydrogen ions into the semiconductor substrate to form a peel layer in part of the semiconductor substrate at a side of the anti-diffusion layer opposite to the gate oxide film; bonding a glass substrate to the surface of the semiconductor substrate where the gate oxide film has been formed; and heat-treating the semiconductor substrate to separate part of the semiconductor substrate along the peel layer.

A light emitting element has: a light emitting layer of semiconductor; and a diffusion layer that has a refractive index equal to or greater than that of the light emitting layer and that diffuses light emitted from the light emitting layer to increase the external radiation efficiency of the light emitting element. The light emitting layer has a refractive index equal to or greater than that of any layers formed between the light emitting layer and the diffusion layer.

There is disclosed a semiconductor light-emitting element comprising a substrate having a first surface and a second surface, a semiconductor laminate formed on the first surface of the substrate and containing a light-emitting layer and a current diffusion layer having a light-extracting surface. The light-emitting element is provided with a light-extracting surface which is constituted by a finely recessed / projected surface, 90% of which is constructed such that the height of the projected portion thereof having a cone-like configuration is 100 nm or more, and the width of the base of the projected portion is within the range of 10-500 nm.

Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

The present invention relates generally to fabricating well performing thin-film batteries onto metallic substrates, polymeric substrates, and doped and undoped silicon substrates. More specifically, the invention may include fabricating an appropriate diffusion barrier layer between the substrate and the battery part of the present invention that separates said two parts chemically during the entire battery fabrication process and the operation and storage conditions of the electrochemical apparatus during its entire lifetime. In one embodiment of the present invention, thin-film batteries fabricated onto a thin, flexible, stainless steel foil substrate using an appropriate diffusion layer show uncompromised electrochemical performance compared to thin-film batteries fabricated onto ceramic substrates when using a 700° C. post-deposition anneal process for the LiCoO2 positive cathode.

An object of the present invention is to simultaneously realize the enlargement of a dynamic range and the downsizing of a pixel. An additional capacitor CS is composed by using: a first capacitor formed of a first diffusion layer, a second diffusion layer and a P well by layering the P well, the first diffusion layer, a first dielectric film, a first polysilicon layer, a second dielectric film and a second polysilicon layer; a second capacitor formed of the second diffusion layer, the first polysilicon layer and the first dielectric film; and a third capacitor formed of the first polysilicon layers, a second polysilicon layer, and a second dielectric film. Thereby, the additional capacitor CS for accumulating carriers overflown from a photodiode PD can secure a required capacitance value while making its size as small as possible.

A MOS type image sensor has an image area that consists of a matrix of pixels and a peripheral circuitry area that drives the image area. To make the MOS type image sensor finer, each of the pixels consists of a second p-well region having a lower impurity concentration than a first p-well region disposed in the peripheral circuitry area; a photodiode having a first main electrode region made of the second p-well region and a second main electrode region formed as a first n-diffusion layer disposed at the surface of the second p-well region; a read transistor having a first main electrode region made of the first n-diffusion layer, a second main electrode region formed as a second n-diffusion layer disposed at the surface of the second p-well region, a gate insulation film disposed on the surface of the second p-well region between the first and second n-diffusion layers, and a gate electrode disposed on the gate insulation film and connected to a read signal line; and an amplification transistor disposed in a third p-well region, having a gate electrode connected to the second main electrode region of the read transistor, a first main electrode region connected to an output signal line, and a second main electrode region. Since the impurity concentration of the second p-well region is low, scaled design rules are employable without causing "white pixels", sensitivity deterioration, signal read voltage increase, or short-channel effect.

A method is provided for manufacturing a component. The method includes forming a diffusion coating on a first intermediate article formed by an additive manufacturing process. The diffusion coating is removed from the first intermediate article forming a second intermediate article having at least one enhanced surface. The diffusion coating is formed by applying a layer of coating material on at least one surface of the first intermediate article and diffusion heat treating the first intermediate article and the layer. The diffusion coating comprises a surface additive layer and a diffusion layer below the surface additive layer. The formation of the diffusion coating and removal thereof may be repeated at least once.

A semiconductor device includes a plurality of PMOS transistors formed on a semiconductor substrate; and a plurality of NMOS transistors formed on the semiconductor substrate. The plurality of PMOS transistors are electrically isolated from each other by a device isolation structure formed in the semiconductor substrate. The plurality of NMOS transistors are continuously formed in a first direction such that a sequence of N-type diffusion layers of the plurality of NMOS transistors extends in the first direction. One of the plurality of PMOS transistors and one of the plurality of NMOS transistors share a gate electrode.

A solar cell and a method of producing the same which realizes electrical separation of the p n junction in a simple manner, and a method of producing a semiconductor device a method of producing a semiconductor device in which an electrode is formed by using a metallic paste material on a substrate covered with a silicon nitride film or a titanium oxide film, wherein a glass paste 104 composed mainly of glass which has a property of melting silicon is provided on an n type diffusion layer 101 in the p n junction; the substrate is baked so that penetration of the n type diffusion layer 101 is effected by the glass paste; aluminum is diffused in the n type diffusion layer 101 below a p electrode 103 formed of an aluminum silver paste to thereby form a p type inversion layer 105 inverted to a p type, whereby the electrical separation of the p n junction can be realized. Further, when a metallic paste material is provided on an insulating film and the metallic paste material is baked, the material penetrates the insulating film to electrically contact with the semiconductor substrate.

An optical film is provided and includes: a transparent support; and a light diffusion layer containing light-transmitting particles and a binder. The light diffusion layer has an average thickness of from 7.5 to 30 μm, and the average thickness of the light diffusion layer is from 1.4 to 3.5 times as large as an average particle diameter of the light-transmitting particles.