The present invention relates to SET / RESET latch circuit,
Schmitt trigger circuit, and MOBILE based D-type
flip flop circuit and
frequency divider circuit using the SET / RESET latch circuit and
Schmitt trigger circuit. Herein, SET / RESET latch circuit is especially configured with CML-type transistors and negative differential resistance diodes. The SET / RESET latch circuit can be applied for very high speed digital circuits A SET / RESET latch circuit, characterized by including a
transistor 1 and 2 in which each emitter of said transistors is commonly connected to a
current source, and a negative differential resistance
diode 1 and 2 which are respectively connected to each collector of said
transistor 1 and 2; and additionally performing to be the relationship of IP<IEE<2·IP(where, IP: the
peak current of said negative differential resistance
diode 1 and 2, IEE: the current of the
current source connected in series to the common node of emitters of said
transistor 1 and 2); and thereby providing a single and differential Non-Return-to-
Zero mode outputs in case that Return-to-
Zero mode SET and RESET voltages are respectively supplied on the base ports of said transistor 1 and 2.