Delay line capable of automatically balancing technological deviations and temperature influences

Abstract

The present invention is a delay line for automatically balancing process deviation and temperature influence, the delay line is connected in series by a plurality of delay units, each of the delay units includes a delay circuit and an inversion circuit; transistors P1, P2, P3, P4 is a PMOS transistor of the same size, and transistors N1, N2, N3, and N4 are NMOS transistors of the same size; the transistors P1, P3, N1, and N3 form one of the delay circuits; the transistors P2, P4, N2, and N4 One of the reverse circuits is formed. The delay line designed by the method of the present invention can automatically adjust the high and low level duty ratio of the delay unit, so that the high and low level duty ratio of the signal is approximately 1 / 2; the delay line designed by the present invention can effectively increase the frequency of the input signal The dynamic range can reduce the locking time of the delay-locked loop; the delay line designed by the invention has a simple structure and adopts standard CMOS electronic devices, which can effectively save chip area and cost.

Description

technical field [0001] The patent of the invention belongs to the field of integrated circuit chips, and in particular relates to a voltage-controlled delay circuit of a delay-locked loop of a chip. Background technique [0002] Delay-locked loops are widely used because of the advantages that phase-locked loops do not have. The biggest advantage of delay-locked loops is that it is easy to achieve precise delay of a certain waveform. There are many practical applications based on this advantage. For example, to shift the phase of a signal by 120 degrees, a three-stage delay unit can be used to delay the delay. The entire delay line is delayed by one cycle, and the output of the first-stage delay unit is the desired signal. For example, to obtain 6 clocks with equal phase intervals, a delay line with 6 stages of delay units can be adopted, and each stage of delay units is delayed by 60 degrees. The delay line is the key and difficult point in the design of the delay locked ...

AI Technical Summary

Problems solved by technology

The structure of the simple delay unit is the NOT gate structure in the digital circuit. This kind of control is simple and can be realized by digital programming. The disadvantage is that the delay time is a discrete value, and the minimum delay is the delay of a NOT gate. The dynamic range of the operating frequency is small. The deviation of the output signal is large

The other is the delay unit with a charge pump structure. This structure has better linearity than the delay unit with a non-gate structure. However, due to the deviation of the chip manufacturing process and the influence of temperature, the delay unit charges and discharges the capacitor at an inconsistent time, and the output signal of the delay unit The high and low level duty cycle will be inconsistent. After the cumulative effect of multi-stage delay units, it will lead to poor phase interval consistency of the delay line output signal, narrow frequency working range, and may even cause the delay locked loop to fail to lock.

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