The present invention provides a
system and method of modifying the
mask layout shapes of an
integrated circuit layout design to compensate for
reticle field location-specific systematic CD variations resulting from
mask writing process variations, lens imperfections in lithographic patterning, and
photoresist process variations. Called PLC (Process-optimized
Layout Compensation), each set of compensation rules according to the present invention is specifically tailored for a particular
mask-writer-patterning-tools-and-
resist-process combination, and are performed on a
reticle-wide basis. Furthermore, for each geometric shape in the mask
layout, the amount of modification is determined based on a
categorization of the type of the shape, the specific location in the
reticle field the particular shape falls in, its context (i.e., surrounding patterns, orientation, etc.), as well as certain
photoresist parameters to be used in the patterning process.