348 results about "Wafer fabrication" patented technology

A method and system are provided that minimize wafer or package level test time without adversely impacting yields in downstream manufacturing processes or degrading outgoing quality levels. The method provides optimization by determining, a priority, the most effective set of tests for a given lot or wafer. The invention implements a method using a processor-based system involving the integration of multiple sources of data that include: historical and realtime, product specific and lot specific, from wafer fabrication data (i.e., process measurements, defect inspections, and parametric testing), product qualification test results, physical failure analysis results and manufacturing functional test results. These various forms of data are used to determine an optimal set of tests to run using a test application sequence, on a given product to optimize test time with minimum risk to yield or product quality.

A method (400) for determining a response to a wafer manufacturing process problem includes the steps of generating a wafer map signature (406) containing defect attributes to be identified and retrieving (410) one or more wafer map signatures from a database. The wafer map signature to be identified is matched (414) with the one or more wafer map signatures from the database in order to help find a root cause of a defect in a wafer manufacturing process.This provides at least the advantage that a signature matching capability allows an Operator to more accurately identify a root manufacturing cause of a wafer defect. Furthermore, instant feedback to the wafer manufacturing process can be provided to facilitate rapid correction of manufacturing errors.

In accordance with the invention, an improved image sensor comprises an array of germanium photosensitive elements integrated with a silicon substrate and integrated with silicon readout circuits. The silicon transistors are formed first on a silicon substrate, using well known silicon wafer fabrication techniques. The germanium elements are subsequently formed overlying the silicon by epitaxial growth. The germanium elements are advantageously grown within surface openings of a dielectric cladding. Wafer fabrication techniques are applied to the elements to form isolated germanium photodiodes. Since temperatures needed for germanium processing are lower than those for silicon processing, the formation of the germanium devices need not affect the previously formed silicon devices. Insulating and metallic layers are then deposited and patterned to interconnect the silicon devices and to connect the germanium devices to the silicon circuits. The germanium elements are thus integrated to the silicon by epitaxial growth and integrated to the silicon circuitry by common metal layers.

A hexagonal single crystal wafer is produced from a hexagonal single crystal ingot. A separation start point is formed by setting a focal point of a laser beam inside the ingot at a predetermined depth from the upper surface of the ingot, which depth corresponds to the thickness of the wafer to be produced, and next applying the laser beam to the upper surface of the ingot while relatively moving the focal point and the ingot to thereby form a modified layer parallel to the upper surface of the ingot and form cracks extending from the modified layer along a c-plane, thus forming a separation start point. The focal point is indexed by relatively moving the focal point in the direction where an off angle is formed and the c-plane is inclined downward.

A new multiresolution analysis (wavelet) assisted reinforcement learning (RL) based control strategy that can effectively deal with both multiscale disturbances in processes and the lack of process models. The application of wavelet aided RL based controller represents a paradigm shift in the control of large scale stochastic dynamic systems of which the control problem is a subset. The control strategy is termed a WRL-RbR controller. The WRL-RbR controller is tested on a multiple-input-multiple-output (MIMO) Chemical Mechanical Planarization (CMP) process of wafer fabrication for which process model is available. Results show that the RL controller outperforms EWMA based controllers for low autocorrelation. The new controller also performs quite well for strongly autocorrelated processes for which the EWMA controllers are known to fail. Convergence analysis of the new breed of WRL-RbR controller is presented. Further enhancement of the controller to deal with model free processes and for inputs coming from spatially distributed environments are also addressed.