Computer-implemented methods, processors, and systems for creating a wafer fabrication process

Abstract

Computer-implemented methods, processors, and systems for creating a wafer fabrication process are provided. One computer-implemented method includes determining individual error budgets for different parameters of the wafer fabrication process based on an overall error budget for the wafer fabrication process and simulated images that illustrate how reticle design data will be printed on a wafer at different values of the different parameters. The method also includes creating the wafer fabrication process based on the overall error budget and the individual error budgets.

Description

PRIORITY CLAIM [0001] This application is a continuation-in-part of U.S. patent application Ser. No. 11 / 048,630 entitled “Computer-Implemented Methods for Detecting Defects in Reticle Design Data,” filed Jan. 31, 2005, which claims priority to U.S. Provisional Application No. 60 / 540,031 entitled “Method and System of Qualifying Integrated Circuit Design for Manufacturability and Application to Improving Critical Dimension Control in Integrated Circuit Manufacturing,” filed Jan. 29, 2004.BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention generally relates to computer-implemented methods for detecting defects in reticle design data. Certain embodiments relate to a computer-implemented method that includes detecting defects in reticle design data using simulated images that illustrate how a reticle will be printed on a wafer at different values of one or more parameters of a wafer printing process. [0004] 2. Description of the Related Art [0005] T...

AI Technical Summary

Benefits of technology

[0018] In one embodiment, the method may include generating an inspection process for the reticle based on results of the detecting step. In one such embodiment, the method may include linking vPWQ data to reticle inspection to drive selective sensitivity of the inspector. In an additional embodiment, the method may include generating an inspection process for the wafer based on results of the detecting step. In one such embodiment, the method may include linking vPWQ data to wafer inspection to drive selective sensitivity of the inspector. In a different embodiment, the method may include fabricating the reticle subsequent to the detecting step, inspecting the reticle, and generating an inspection process for the wafer based on results of the detecting step and the inspecting step. In this manner, the method may include linking the combination of vPWQ and reticle inspection data to wafer inspection to drive selective sensitivity of the wafer inspector. In another embodiment, the method may include fabricating the reticle subsequent to the detecting step, inspecting the reticle, and generating an inspection process for the wafer based on results of the detecting step, results of the inspecting step, critical feature data generated by a designer of the reticle design data, or some combination thereof. As such, the methods may include linking the combination of vPWQ, reticle inspection, and / or critical features identified by the designer to drive wafer inspection sensitivity, metrology sample plans and critical dimension (CD) control systems for optimal yield.

Problems solved by technology

Consequently, defects that are formed on a wafer during lithography may be particularly problematic for the integrated circuit manufacturing process.

However, as the dimensions of integrated circuits decrease and the patterns being transferred from the reticle to the wafer become more complex, defects or marginalities in the features formed on the reticle become increasingly important.

In particular, if the pattern is not formed accurately on the reticle, such discrepancies increasingly produce defects on the wafer as the dimensions of the pattern decrease and the complexity of the pattern increases.

In addition, marginalities in the reticle design may cause the design to print incorrectly on the wafer.

These efforts are relatively complex and difficult due, at least in part, to the fact that not all discrepancies or marginalities in the pattern formed on the reticle (as compared to the ideal pattern) will cause errors on the wafer that will adversely affect the integrated circuit.

In other words, some error in the pattern formed on the reticle may not produce defects on the wafer at all or may produce defects on the wafer that will not reduce the performance characteristics of the integrated circuit.

Therefore, one challenge of many in developing adequate methods and systems for qualifying a reticle pattern is to discriminate between pattern defects or marginalities that “matter” and those that do not.

However, conventional DRC operates only at the nominal process conditions, or at most, at a limited number of process conditions and / or at a limited number of points within the device.

However, this method is designed to determine only the best focus and exposure settings and not to explore the full range of the process window conditions available for each design.

Therefore, such software methods have several disadvantages.

In particular, these software methods do not examine the full range of process window conditions thereby failing to detect process window marginalities and missing potential defects.

In addition, these methods do not determine the exact focus and exposure conditions under which defects will occur thereby preventing the complete optimization of the design.

The lack of complete process window information also limits the ability to implement advanced process control techniques for critical dimension control across all critical features on the device.