The invention discloses a manufacturing method of a twin-
transistor and zero-
capacitance dynamic RAM (
Random Access Memory), aiming at providing the manufacturing method of the twin-
transistor and zero-
capacitance dynamic RAM which is manufactured by adopting a
silicon of insulator-based gate-last process and has a
design for manufacturability. In the process, the characteristics different from the characteristics of greater Overlap between a T1 source / drain
electrode and a gate and greater distance Underlap between a T2 source / drain
electrode and the gate in a conventional
CMOS (Complementary
Metal-
Oxide-
Semiconductor Transistor) process are effectively achieved by self aligning; the manufacturing method is suitable for manufacturing of an
integrated circuit in the gate-last process of a high-
dielectric-constant oxidation layer
metal gate of below 45nm; and by adjusting work functions of the gates of the T1 and the T2, which are close to the source
electrode and the drain electrode, or
doping types of channel regions at the lower parts of the gates, which are close to the source electrode and the drain electrode through
ion implantation, the channel regions in the channel regions of the T1, which are close to the source electrode and the drain electrode, are inverted to be the same types with the source region and the drain region under the condition of no increase of the pressure of the gates and
diffusion regions below the gates of the source electrode and the drain electrode of the T2 are inverted into the opposite types of the source region and the drain region under the condition of no increase of the pressure of the gates.