Graph pattern decomposition method adopting triple patterning photoetching technology

Abstract

The invention belongs to the field of design for manufacturability of semiconductor photoetching technologies, and particularly relates to a graph pattern decomposition method adopting a triple patterning photoetching technology. The method comprises steps of firstly, establishing a conflict graph through a rectangle expansion method, then randomly producing a three-colored initial solution, fixing one color in each turn of optimization, performing two-colored optimization on a conflict sub-graph of the rest two colors through a double patterning pattern distribution method, repeating the iterative optimization process until the current optimum solution is not undated for multiple times, and finally, repeatedly calling the above steps and selecting an optimal three-colored result as an output result. According to method, the existing double patterning pattern distribution method is adopted, an optimal strategy obtained through multiple computation is adopted, and a globally optimal solution is searched, so that the purpose of distributing a graph pattern through the triple patterning photoetching technology is realized.

Description

technical field [0001] The invention belongs to the field of manufacturability design of semiconductor lithography process, and specifically relates to a layout pattern decomposition method of triple exposure lithography process. In this method, dense layout patterns are distributed to three different masks, which can meet the requirements of semiconductor Photolithography process requirements. Background technique [0002] The prior art discloses that the photolithography process is one of the key processes in the integrated circuit manufacturing process. As the feature size of integrated circuits continues to shrink, the layout pattern density continues to increase, but the wavelength of the light source used in lithography has not been significantly reduced, and the exposure resolution has not been significantly improved, resulting in pattern conflicts on the same mask. ) is increasing in number. The pattern conflict is defined as a distance between two layout patterns ...

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Problems solved by technology

How to assign the GDSII design layout patterns to multiple different masks, so that the pattern conflicts on the same mask are the least, is the key to the multi-exposure layout allocation method; at the same time, in order to reduce the number of conflicts, the same layout pattern may It will be divided and assigned to different masks, and the division points on the same pattern are called stitches; practice shows that too many stitches will lead to a decrease in chip yield

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