19081results about "Cable/conductor manufacture" patented technology

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

A method for fabricating an optical interference display cell is described. A first electrode and a sacrificial layer are sequentially formed on a transparent substrate and at least two openings are formed in the first electrode and the sacrificial layer to define a position of the optical interference display cell. An insulated heat-resistant inorganic supporter is formed in each of the openings. A second electrode is formed on the sacrificial layer and the supporters. Finally, a remote plasma etching process is used for removing the sacrificial layer.

The invention discloses a transparent conduction film, a conduction structure thereof and a preparation method of the transparent conduction film. The transparent conduction film is of a single-sided dual-layer conduction structure. The conduction structure comprises a first metal embedding layer and a second metal embedding layer, wherein the first metal embedding layer is formed by impressing on a substrate or impressing on a polymer layer on the surface of the substrate; and the second metal embedding layer is formed by coating the polymer layer on the surface of the first metal embedding layer through impressing, the first layer of conduction structure and the second layer of conduction structure have a grid groove structure, and conductive materials are filled in grooves. The single-sided graphical transparent conduction film provided by the invention has the advantages of high resolution and transmittance, independent and adjustable sheet resistance, and the like. According to the transparent conduction film, the cost can be reduced, and the weight and the thickness of a manufactured touch panel can be reduced.

An optical electrical hybrid cable for transmitting an optical signal and an electrical signal simultaneously is provided. The optical electrical hybrid cable includes a fiber-optic cable disposed in the center of the optical electrical hybrid cable, and including a plurality of tubes each of which comprises a plurality of optical fibers operatively mounted in an inner space thereof, and a first binder disposed around the plurality of tubes, a plurality of power cables disposed around the fiber-optic cable, each of the power cables comprising a plurality of conducting wires, and a second binder disposed around the plurality of power cables.

A novel method of designing and fabricating flexible and lightweight cable [100] having a central conductor [110], a dielectric layer [130], an outer conductor [150] and an insulation coating [170] using thin film technology is disclosed. The dielectric layer [130] is ‘grown’ on dielectric layer [130] using electrophoretic deposition to a specified thickness, based upon its intended use. It may include nano-diamonds. Ion beam assisted deposition is used to metalize the cable dielectric layer [130]. This may be ion beam assisted sputtering, ion beam assisted evaporative deposition or ion beam assisted cathodic arc deposition. In an alternative embodiment, the outer conductor may be etched to provide greater flexibility, or to add a piezoelectric layer. The central conductor [110] may be created from dielectric fibers [113] which are metalized as described above. The piezoelectric layer added to create ultrasonic transducer cables.

The invention relates to a telecommunications cable module comprising at least one optical fiber surrounded by a protective skin of a thermoplastic elastomer having flexible diol segments, and in particular a polyester thermoplastic elastomer. In the invention, the thermoplastic elastomer having flexible diol segments presents a melting point greater than 130° C. and an initial resistance to tearing less than 60 kN / m. The material proposed by the invention is easily applied to fibers, in particular by extrusion.

MEMS Device Having Contact and Standoff Bumps and Related Methods. According to one embodiment, a movable MEMS component suspended over a substrate is provided. The component can include a structural layer having a movable electrode separated from a substrate by a gap. The component can also include at least one standoff bump attached to the structural layer and extending into the gap for preventing contact of the movable electrode with conductive material when the component moves.

A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. The chemical reaction resulting from the combination produces reactants which etch the patterned heterogeneous structures to produce, in embodiments, a thin residual structure exhibiting little deformation. The methods may be used to conformally trim silicon oxide while removing little or no silicon, polysilicon, silicon nitride, titanium or titanium nitride. In an exemplary embodiment, the etch processes described herein have been found to remove mold oxide around a thin cylindrical conducting structure without causing the cylindrical structure to significantly deform.

Methods of dry etching silicon-containing dielectric films are described. The methods include maintaining a relatively high temperature of the dielectric films while etching in order to achieve reduced solid residue on the etched surface. Partially or completely avoiding the accumulation of solid residue increases the etch rate.

A membrane comprising: (a) a hydrophobic matrix polymer, and (b) a hydrophilic non-ionic polymer, wherein the hydrophobic polymer and the hydrophilic polymer are disposed so as to form a dense selectively proton-conducting membrane. The microstructure of such a membrane can be tailored to specific functionality requirements, such as proton conductivity vs. proton selectivity, and selectivity to particular species.

A method for forming self-assembled patterns on a substrate surface is provided. First, a block copolymer layer, which comprises a block copolymer having two or more immiscible polymeric block components, is applied onto a substrate that comprises a substrate surface with a trench therein. The trench specifically includes at least one narrow region flanked by two wide regions, and wherein the trench has a width variation of more than 50%. Annealing is subsequently carried out to effectuate phase separation between the two or more immiscible polymeric block components in the block copolymer layer, thereby forming periodic patterns that are defined by repeating structural units. Specifically, the periodic patterns at the narrow region of the trench are aligned in a predetermined direction and are essentially free of defects. Block copolymer films formed by the above-described method as well as semiconductor structures comprising such block copolymer films are also described.

The invention relates to a method of forming a conducting nanowire between two contacts on a substrate surface wherein a plurality of nanoparticles is deposited on the substrate in the region between the contacts, and the single nanowire running substantially between the two contacts is formed by either by monitoring the conduction between the contacts and ceasing deposition at the onset of conduction, and / or modifying the substrate to achieve, or taking advantage of pre-existing topographical features which will cause the nanoparticles to form the nanowire. The resultant conducting nanowires are also claimed as well as devices incorporating such nanowires.

Device for generating a plasma discharge for patterning the surface of a substrate, comprising a first electrode having a first discharge portion and a second electrode having a second discharge portion, a high voltage source for generating a high voltage difference between the first and the second electrode, and positioning means for positioning the first electrode with respect to the substrate, wherein the positioning means are arranged for selectively positioning the first electrode with respect to the second electrode in a first position in which a distance between the first discharge portion and the second discharge portion is sufficiently small to support the plasma discharge at the high voltage difference, and in a second position in which the distance between the first discharge portion and the second discharge portion is sufficiently large to prevent plasma discharge at the high voltage difference.

Methods and apparatus for protecting the thin films during chemical and / or thermal edge strengthening treatment. In one embodiment, a portion of each individual sheet is laminated. Pairs of sheets are then sealed together such that the thin film sides face inward to form a thin film sandwich. In some embodiments, the sandwich in then immersed in a chemical strengthener. In other embodiments, a localized treatment is applied to the unstrengthened edges.

A method for fabricating an IC support for supporting a first IC die connected in series with a second IC die; the IC support comprising a stack of alternating layers of copper features and vias in insulating surround, the first IC die being bondable onto the IC support, and the second IC die being bondable within a cavity inside the IC support, wherein the cavity is formed by etching away a copper base and selectively etching away built up copper.

A process for the etching of multiple layers of at least two different metals comprisies:forming a resist pattern over a first layer of metal, said resist pattern having a pattern of openings therein, applying a first etch solution onto said resist pattern so that at least some etch solution contacts exposed areas of the first layer of metal, etching away the majority of the depth of the first metal in exposed areas of metal in the first layer of metal, applying a second etch solution onto the resist pattern the second etch solution having a rate of etch towards the first metal as compared to the first etch solution that is at least 20% less than the millimeter / minute rate of etch of the first etch solution at the same etch solution temperature, removing the second etch solution from said resist pattern after at least the first metal layer has been etched sufficiently to expose areas of a second metal layer underlying the first metal layer by forming an etched first metal layer, and applying a third etch solution to said etched first metal layer, the third etch solution having a faster rate of etch towards the second metal than towards the first metal to etch into said second metal layer without destroying the etched first metal layer.

Glass interposer panels and methods for forming the same are described herein. The interposer panels include a glass substrate core formed from an ion-exchangeable glass. A first layer of compressive stress may extend from a first surface of the glass substrate into the thickness T of the glass substrate core to a first depth of layer D1. A second layer of compressive stress may be spaced apart from the first layer of compressive stress and extending from a second surface of the glass substrate core into the thickness T of the glass substrate core to a second depth of layer D2. A plurality of through-vias may extend through the thickness T of the glass substrate core. Each through-via is surrounded by an intermediate zone of compressive stress that extends from the first layer of compressive stress to the second layer of compressive stress adjacent to a sidewall of each through-via.