49 results about "NvSRAM" patented technology

An nvSRAM having a stacked oxide layer is disclosed. A disclosed device comprises: two NMOS transistors and two PMOS transistors for an SRAM latch; two NMOS pass gates for reading and writing a HIGH condition and a LOW condition that are formed in the SRAM latch; and two floating gate NVM devices of split gate structure for storing the HIGH condition and the LOW condition that are stored in the SRAM latch when the power is off.

A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.

The invention relates to a computer remote control method and a computer system, wherein a remote communication module is employed to communicate, and a starting bit zone of a bit zone loading module is changed and a restart/or start command is sent to the computer; the starting bit zone is checked by a basic input and output system, if the starting bit zone is set as a bit zone for starting the second operation system, then the second operation system in a storage apparatus will be started; then the computer can be operated by a running second operation system. Said remote communication module is a BMC chip, said bit zone storage module is a F/W module of the BMC chip; and said storage apparatus is a nonvolatile memory NVSRAM. By using the scheme, a remote complete control can be implemented, the remote diagnosis and network function of the second operation system can restore and re-install the operation system and repair the operation system malfunctions apart from the physical damage of the motherboard.

This invention discloses a low-voltage fast-write 12T or 14T PMOS NVSRAM cell structure which comprises a 6T LV SRAM cell and one pairs of two 3T or 4T HV PMOS Flash strings. Due to reverse threshold voltage definition of PMOS and NMOS flash cell, this PMOS NVSRAM cell has the advantage over the NMOS NVSRAM cell to have the same data polarity between SRAM and Flash pairs during the data writing operation. In addition, this PMOS NVSRAM's PMOS Flash cell uses similar low-current FN-tunneling scheme as NMOS NVSRAM, thus the fast data program and erase can be achieved in a big density up to 100 Mb simultaneously. As a result, low power voltage operation of NVSRAM with 1.2V VDD can be much easier to be designed without coupling the FSL line to any VDD level during the flash data loading into SRAM cell during a power-on period.

A non-volatile static random access memory (NVSRAM) device includes a volatile circuit and a non-volatile circuit. Under normal operations when an external power is supplied, the volatile circuit can provide fast data access. When the power supply is somehow interrupted, the non-volatile circuit can provide data backup using an inverter circuit and a non-volatile erasable programmable memory (NVEPM) circuit, thereby retaining data previously stored in the volatile circuit.

An integrated circuit (IC) device includes a static random access memory (SRAM) array, and a resistive memory (resistive memory) array. A first set of programmable resistive elements in the resistive memory array are used to store data from memory cells in the SRAM array. Sense amplifier circuitry is couplable to the SRAM array and the resistive memory array. An arbiter is configured to assert an resistive memory enable signal to couple the sense amplifier circuitry to the resistive memory array and decouple the sense amplifier circuitry from the SRAM array during a resistive memory read operation, and to couple the sense amplifier to the SRAM array and decouple the sense amplifier circuitry from the resistive memory array during an SRAM read operation.

This invention discloses several embodiments of a low-voltage fast-write NVSRAM cells, made of either of a 2-poly floating-gate type flash cell or a 1-poly charge-trapping SONOS or MONOS flash cell with improvement by adding a Bridge circuit. This Bridge circuit is preferably inserted between each LV 6T SRAM cell and each HV Flash cell that comprises one paired complementary Flash strings. The Flash strings can be made of either 2T or 3T Flash strings. The tradeoff of using either a 2T or a 3T Flash string is subject to the gate area penalty and required design specs. One improvement for adding the Bridge circuit into the NVSRAM cell is to ensure the data writing between Flash cell and SRAM cell with the same polarity and to allow the operation down to low 1.2V Vdd.

Two on-chip capacitors including one HV capacitor VPPcap and one LV VCC capacitor VCCcap are built over a NVSRAM memory chip as a back-up second power supplies for each NVSRAM cell, regardless of 1-poly, 2-poly, PMOS or NMOS flash cell structures therein. The on-chip HV and LV capacitors are preferably made from one or more MIM or MIP layers for achieving required capacitance. A simplified VCC power system circuit without a need of a State machine designed for performing only one NVSRAM Program operation without Erase operations is proposed for initiating NVSRAM's Auto-Store operation without using any off-chip Vbat and Vcap. During the Auto-Store operation, all HV pumps and oscillators associated with the two on-chip capacitors are shut off once VCC voltage drop is detected by a VCC detector to be below 80% of regular VDD level.

The invention discloses a reconfigurable computing storage fusion flash memory control system which comprises a host interface, a flash memory medium interface, an embedded processor, a cache and storage controller, an on-chip FLASH, an NVSRAM and an embedded FPGA, and all hardware modules are mounted on an internal bus and communicate through the internal bus. And the embedded FPGA is used for calculating hardware acceleration of tasks, generating a bit stream file in a software environment and reburning the bit stream file, changing the internal structure of the embedded FPGA, arranging andwiring the embedded FPGA, realizing different functions and realizing a reconfigurable hardware acceleration function. The method solves the problems of bandwidth wall and high power consumption caused by separation of calculation and storage and the technical problem of chip tape-out function solidification, has the advantages of being programmable, flexible in design, capable of achieving onlineupgrading and secondary development and the like, and can achieve calculation in storage, reduce data movement and reduce power consumption; and the chip hardware is reconfigurable and supports realization of different functions.

Systems and methods for transferring data. A circuit transfers information between two buses using different signal voltage levels and multiplexes signals applied to the second bus over multiple devices coupled thereto. The data on a first data bus is transferred at a first voltage level and the data on a second data bus is transferred at a second voltage level. For example, the first data bus may transfer data at 3.3V and the second data bus may transfer data at 5V. A logic device (e.g., a CPLD) is connected between the first and the second data buses for transferring the data between the first and second voltage levels. The logic device is also configured for multiplexing the data with the second voltage level between first and second devices (e.g., one or more LEDs and/or NVSRAMs) connected to the second data bus.

The present invention discloses a 10T NVSRAM cell with a 6T SRAM cell with 4T Flash cell with one dedicated Flash-based Charger. In addition, a Pseudo-8T NVSRAM cell with a shared Flash-based Charger between two adjacent 8T NVSRAM cells at top and bottom in cell layout is also disclosed to further reduce cell size by 20%. As opposed to the prior art of 12T NVSRAM cell, the Store operation of the above two preferred embodiments use a DRAM-like charge-sensing scheme with Flash cell configured into a voltage follower ensured by the Flash-based Charger to obtain the final ΔV_Q-QB>0.2V at Q and QB nodes of each SRAM cell to cover all the mismatched of parasitic capacitance in flash cell devices and layout for a reliable amplification by ramping up SRAM's VDD line and ramping down SRAM's VSS line.