30results about How to "With programmable" patented technology

The invention relates to a high-speed and high-precision digital pulse generating circuit and a pulse generating method. The digital circuit can generate programmable reference pulses and variable pulse sequences, and adjust the pulse width and pulse in each pulse sequence with precise timing steps. Phase offset between sequences. This circuit has a timing step automatic calibration function, which can adapt to the influence of a wide range of temperature changes and changes in power supply. It is composed of system clock input circuit, register control circuit, system clock pulse timer circuit, loop oscillator pulse timing circuit, logic unit delay pulse timing circuit and pulse output circuit. It has the characteristics of high speed and high precision. Realized, cost-effective, can be used in electronic measurement, semiconductor testing, radar control and high-precision industrial measurement and control fields.

The invention relates to the field of PCB coding, and provides a direct coding method for a PCB. The direct coding method comprises the following steps: directly coding the PCB by using a carbon dioxide laser, wherein the size of the focus light spot of the carbon dioxide laser is equal to or smaller than 0.14 mm; aiming at two-dimensional codes or one-dimensional codes in different sizes requested on different PCBs, coding is realized by controlling the power of the carbon dioxide laser and selecting different coding modes. The high-precision, high-speed and programmable carbon dioxide laser is adopted to directly code the PCB, aiming at two-dimensional codes or one-dimensional codes in different requested sizes, the coding depth can be controlled by controlling the power of the carbon dioxide laser, and appropriate coding modes are selected, so that the PCB is not damaged in the coding process, automation can be achieved in the production process, and the labor and the materials can be saved; laser coding is not affected by assembling steps or environment, can be directly acted on the PCB, and the process lasting property is good, so that the effect that the code lasts for the whole life of the PCB is achieved.

The invention discloses an integrated circuit structure special for a specific application algorithm. The structure comprises at least one processor which can be configured with an operational unit, and at least one processor which can be configured with a storage component, wherein the processor which can be configured with the operational unit or the processor which can be configured with the storage component is mutually connected with at least one of the processor which can be configured with the operational unit and the processor which can be configured with the storage component; the processor which can be configured with the operational unit comprises a first algorithm data control component and at least one operational unit, and the first algorithm data control component executes a configuration instruction and configures the operation function of the operational unit; and the processor which can be configured with the storage component comprises a second algorithm data control component and at least one storage component, and the second algorithm data control component executes the configuration instruction and configures the storage function of the storage component. Thestructure has the advantages of flexibility of configurability and programmability, simple and convenient operation, and good algorithm confidentiality.

The invention discloses an inverter control circuit with constant pulse width output and its operating mode, which are used to realize the unipolar operation of the inverter. The inverter control circuit is composed of eight parts: a sampling module, an inverter, a microprocessor dsPIC, a reference voltage generating module, a summing and integrating module, a comparing and exclusive OR module, a monostable trigger and a driving circuit. Under the control of the circuit, the output pulse width of the inverter is constant, which is equal to the transient state maintenance time of the monostable trigger. The time of each cycle is controlled by the reference voltage, the sum and integral module and the comparison XOR module, and the output voltage is equal to the reference voltage in one cycle. The control circuit has the advantages of good input voltage adjustment, strong robustness, strong ability to suppress load changes, and simple control. It does not require an accurate mathematical model. The magnitude and frequency of the inverter output voltage are continuously adjustable, and the output sinusoidal voltage High precision.

The invention discloses a sweep signal generator, which comprises a parameter command receiving port, a sweep frequency control parameter generating unit, a sweep frequency control word random access memory (RAM), an RAM read address generator, a parameter regulating unit, a phase accumulator, a carrier address accumulator, a carrier sheet RAM, an adder, an analog-digital converter and a low pass filter. A method of superposing two paths of frequency components is adopted, namely a method for adding a frequency base unit weight part of a sweep signal and a frequency increment part of the sweep signal is utilized to generate the sweep signal, and the accuracy and frequency resolution of the generated sweep signal are greatly improved. The sweep signal generator has the highest accuracy of 1uHz. Moreover, a digital signal processor (DSP), a field programmable gate array (FPGA) and other digital processing modes are adopted, so the characteristics of programmability and high speed are achieved, the DSP, FPGA and the like can be integrated on a printed circuit board (PCB) and are not required to be connected through extra connecting lines, and the external interference can be reduced.

The invention discloses a novel electric water pump, and the novel electric water pump comprises a motor and a water pump, the motor is fixedly connected to the water pump, the motor comprises a drive part and a control part, the control part comprises a fixing shell, a chip plate is formed in the fixing shell, the chip plate is fixedly connected to the fixing shell, the chip plate is provided with an integrated chip, the integrated chip is fixedly connected to the chip plate, the drive part comprises a brushless stator and a brushless rotor, the brushless stator is sleeved out the brushless rotor. The novel electric water pump has the characteristic of compact structure, reliable and simple use, low noise, saving on energy and environment friendly, intelligent control and programming, also has the function of water out protection, overload protection, reverse connection protection and speed adjustment, the fault of the pump can be reduced, the use efficiency and reliability of the novel pump can be raised and the water pump and the motor can be effectively protected.

The invention relates to the technical field of analog integrated circuits, in particular to a calibration circuit design method for pipeline ADCs. The present invention mainly includes: establishing a pipelined ADC behavior level model, constructing the quantitative relationship between ADC analog circuit design parameters and digital calibration circuit design parameters and ADC performance; obtaining analog circuit design parameters and digital calibration circuit design that minimize ADC power consumption parameters; design the circuit according to the obtained parameters; obtain the calibration coefficient through the calibration algorithm and the reference DAC; write the calibration coefficient into the digital calibration circuit. The beneficial effect of the present invention is that the calibration circuit is greatly simplified, and all of them are implemented on-chip, so the power consumption and area are extremely small, compared with the traditional on-chip background calibration circuit, the power consumption and area are saved by more than 50%; the calibration circuit only increases the ADC core 10% of the area and 5% of the power consumption, so basically no additional chip area and power consumption; at the same time, the calibration system can be adjusted to adapt to different working environments.

The invention discloses a deep packet detection system and method based on a software defined network, and relates to the field of deep packet detection. The deep packet detection system includes network equipment which supports a DPI function, a DPI controller and a DPI server, wherein the network equipment which supports the DPI function is used for processing the part of the second layer to the fourth layer of a deep packet detection rule, the DPI server is used for processing the part above the fourth layer of the deep packet detection rule, and the DPI controller is used for controlling and coordinating the whole deep packet detection system, including the steps of synchronizing flow tables, configuring the network equipment which supports the DPI function and the deep packet detection rule on the DPI server, and coordinating the network equipment which supports the DPI function and the DPI server. The deep packet detection system based on the software defined network can improve the utilization rate of resources, and can also realize effective control of a DPI system, and the functions and performance of the DPI system are enhanced.

The embodiment of the invention provides a data transmission system and a programmable serial peripheral interface controller. The data transmission system comprises a serial peripheral interface and a programmable controller. The serial peripheral interface is coupled between a first device and at least one second device. The programmable controller is used for controlling the serial peripheral interface to be switched between a single-port data transmission mode and a multi-port data transmission mode, wherein when more than one second device is coupled to the serial peripheral interface, the serial peripheral interface is switched to the multi-port data transmission mode and used for controlling multi-port data transmission between the first device and the second device, the first device simultaneously transmits data to each second device through a first transmission bus end of the serial peripheral interface, and the first device simultaneously receives data from each second device through a second transmission bus end of the serial peripheral interface.

The invention relates to a UWB radar signal simulator based on FPGA, comprising a PC104 interface module, an RAM module, an FPGA module and a high-speed DAC module; the PC104 interface module completes data transmission with a host with PC104 mode by a PCI protocol; the RAM module adopts six ZBT-SRAMs with the bit width of 32 as data cache; the FPGA module adopts Virtex-4 series of product XC4VLX40 offered by Xilinx company and comprises a PCI interface control module, a RAM control module, a high-speed DAC control module and a radar waveform control module; the high-speed DAC control module selects AD9736 of ADI company; the interconnection of all the modules is realized by control modules in the FPGA module, the PC104 interface control module completes butting joint of the FPGA module and the PC104 interface module; data generated by controlling a host computer is transmitted to the inner part of the FPGA module from the PC 104 interface module; the RAM control module completes butting joint of the FPGA module and the RAM module so as to realize the transmission of data between the FPGA and the ZBT-SRAM; and the high-speed DAC control module completes butting joint of the FPGA module and the high-speed DAC module and controls the high-speed DAC module to generate various radar waveforms.

The invention discloses a controlled dual-output bootstrap circuit, which comprises a sequential control circuit unit, a basic bootstrap circuit unit and a bootstrap output voltage control unit. The controlled dual-output bootstrap circuit solves the problem that the bootstrap output voltage in the conventional bootstrap circuit descends slowly with time, and the linearity of the bootstrap outputvoltage is improved by 20 dB; on the basis of a basic bootstrap circuit, the controlled dual output of the bootstrap output voltage is realized effectively by adding NMOS pipes NM7, NM8 and NM 9 and PMOS pipes PM5, PM6, PM7 and PM8. The controlled dual-output bootstrap circuit can be widely applied to variable-gain sample-and-hold circuits in high-speed and high-precision analog-digital converters.

The invention discloses an FPGA based multi-board-card array parallel decoding device and method. The device, adopting a CPCI communication framework, comprises a main control card used for communicating with the exterior and carrying out management scheduling control for a decoded card, more than six decoding cards used for decoding fast operation and reporting an operation result and a back plate used for the decoding cards and the main control card to finish high-speed interconnection of the board cards; the parallel decoding device adopts an ARM processor to take charge of state management inside each board card and configuration uploading of am FPGA firmware, and transmits the state information to a PC (Principal Computer) through an internal network path; and the PC controls and schedules based on related states. The decoding device makes a full use of the high-speed serdes interface of the FPGA, so that the data transmission bandwidth is improved and the data transmission time is reduced; and each board card is internally provided with a high-speed big-capacity memory DDR3 unit, so that high-speed storage and access of data is guaranteed.