A calibration circuit design method for pipeline adc

Abstract

The invention relates to the technical field of analog integrated circuits, in particular to a calibration circuit design method for pipeline ADCs. The present invention mainly includes: establishing a pipelined ADC behavior level model, constructing the quantitative relationship between ADC analog circuit design parameters and digital calibration circuit design parameters and ADC performance; obtaining analog circuit design parameters and digital calibration circuit design that minimize ADC power consumption parameters; design the circuit according to the obtained parameters; obtain the calibration coefficient through the calibration algorithm and the reference DAC; write the calibration coefficient into the digital calibration circuit. The beneficial effect of the present invention is that the calibration circuit is greatly simplified, and all of them are implemented on-chip, so the power consumption and area are extremely small, compared with the traditional on-chip background calibration circuit, the power consumption and area are saved by more than 50%; the calibration circuit only increases the ADC core 10% of the area and 5% of the power consumption, so basically no additional chip area and power consumption; at the same time, the calibration system can be adjusted to adapt to different working environments.

Description

technical field [0001] The invention relates to the technical field of analog integrated circuits, in particular to a calibration circuit design method for pipeline ADCs. Background technique [0002] ADC converts analog signals into digital signals, and is widely used in various electronic systems such as communication, signal processing, and storage, and plays an irreplaceable role. At present, with the rapid development of electronic information technology, the market urgently needs high-speed, high-precision, low-voltage and low-power ADCs that can be integrated with digital circuits. Pipeline ADC has become the focus and hotspot of research at home and abroad because of the good compromise between speed, precision and power consumption. [0003] The conversion accuracy of the pipeline ADC is affected by many errors in the circuit, mainly including: thermal noise, clock jitter, switch on-resistance non-linearity, capacitance mismatch, operational amplifier (hereinafter ...

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Problems solved by technology

[0005] At present, the present invention proposes a calibration circuit design with low power consumption, on-chip integration (SoC) and programmable calibration coefficients in order to solve the problems of too much power consumption, too complicated implementation and too slow calibration speed of the above-mentioned existing calibration circuit method

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