155results about How to "Increase channel length" patented technology

The semiconductor device of this invention has unit cells, each of which includes: a substrate; a drift layer on the substrate; a body region in the drift layer; a first doped region of a first conductivity type in the body region; a second doped region of the first conductivity type arranged adjacent to the body region and in a surface region of the drift layer; a third doped region of the first conductivity type arranged between two adjacent unit cells' second doped region of the first conductivity type and in the surface region of the drift layer to contact with the second doped region of the first conductivity type; a gate insulating film arranged to contact with the surface of the drift layer at least between the first and second doped regions of the first conductivity type; a gate electrode on the gate insulating film; and first and second ohmic electrodes. The dopant concentration of the third doped region of the first conductivity type is lower than that of the second doped region of the first conductivity type and equal to or higher than that of the drift layer.

A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source / drain region is formed in the fin active region of both sides of a gate electrode.

A method of estimating a channel length (304) in a wireless receiver is disclosed. The receiver receives a signal (122) from a remote transmitter. The receiver selects a plurality (K) of different candidate channel lengths and determines a respective criterion value (402) of the signal for each of the plurality of different candidate channel lengths. The receiver selects a channel length (410) from the plurality of different candidate channel lengths in response to the respective criterion value (404).

A split gate flash memory is provided. Trenches are formed in the substrate to define active layers. The device isolation layers are formed in the trenches. The surface of the device isolation layers is lower than the surface of the active layers. The stacked gate structures each including a tunneling dielectric layer, a floating gate and a cap layer are formed on the active layers. The inter-gate dielectric layers are formed on the sidewalls of the stacked gate structures. The select gates are formed on one side of the stacked gate structure and across the active layer. The select gate dielectric layers are formed between the select gates and the active layers. The source regions are formed in the active layers on the other side of the stacked gate structures. The drain regions are formed in the active layers on one side of the select gates.

A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.

A semiconductor device and a method of forming the semiconductor device are provided. The semiconductor device may include, but is not limited to, a semiconductor substrate and a third array of semiconductor elements. The semiconductor substrate may include a first array of separate grooves, a second array of separate active regions, and at least an isolating region, the isolating region separating the separate active regions from each other. Each separate groove extends in the separate active region and does not extend over the isolating region. The third array of semiconductor elements is provided on the semiconductor substrate. Each of the semiconductor elements has an electrically conductive portion that is provided in the separate groove. The semiconductor element may be a trench gate transistor, and the electrically conductive portion may be a gate electrode.

The cooling air introducing port 24 is open to a lower portion of an axial direction end portion of the motor housing member 11, 12, the water-proof cover 25 for covering the cooling air introducing port 24 is attached to the outside of the axial direction end portion of the housing member 11, 12, and the air introducing passage 26 having a labyrinth structure is composed of the bent portion 25d provided in a lower end portion of the water-proof cover 25, the first wall face 21d provided in the annular portion 21b of the shroud and the second wall face 21e.

A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate to form an isolation layer defining an active region; forming a recess within the active region; forming a metal layer filling the recess; asymmetrically etching the metal layer to form an asymmetric gate having a stepped top surface at a predetermined portion of the recess; and forming a capping oxide layer filling a remaining portion of the recess where the asymmetric gate is not formed, thereby obtaining an asymmetric buried gate including the asymmetric gate and the capping oxide layer.

A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess pattern and the hard mask pattern, etching a bottom surface of the first recess pattern exposed by the passivation layer to form a second recess pattern, oxidizing sidewalls of the second recess pattern to form a silicon oxide layer, removing the passivation layer and the silicon oxide layer in sequential order, and forming a gate pattern over an intended recess pattern including the first recess pattern and the second recess pattern.

A method for fabricating a semiconductor memory device with a vertical channel transistor includes forming a plurality of pillars each having a hard mask pattern thereon over a substrate, each of the plurality of pillars comprising an upper pillar and a lower pillar; forming a surround type gate electrode surrounding the lower pillar; forming an insulation layer filling a space between the pillars; forming a preliminary trench by primarily etching the insulation layer using a mask pattern for a word line until a portion of the upper pillar is exposed; forming a buffer layer over a resultant structure including the preliminary trench except on a bottom of the preliminary trench; and forming a trench for a word line by secondarily etching the insulation layer until the surround type gate electrode is exposed.

The present invention discloses a compliant banding system for use in a marine environment comprising a flexible compliant member and an abaxial relatively rigid strap, both constructed to extend circumferentially around an underlying structure such as a strake or fairing collar. The strap maintains a fixed circumference while the compliant member flexes intermediate the strap and an underlying.

The present invention lengthens gate conductors used in memory chips to limit leakage current, while still allowing the overall size of cells to remain the same. The channel length for each gate is increased by decreasing the size of spaces between gates. Decreases in space size occurs by using photolithographic image enhancement techniques. These techniques allow the space between gate conductors to be smaller while the gate size increases. In addition, a groove may be added that additionally lengthens the effective channel length and provides an additional electrical shield to limit leakage current. These techniques lead to the same density memory cells for a given process with less leakage. Finally, if grooved gate structures are used, having a longer gate conductor allows a three sigma process to be used, which increases yields.

A method for fabricating a semiconductor device having a flask type recess gate includes forming a hard mask pattern on a substrate, etching the substrate to a predetermined depth using the hard mask pattern to form a first recess pattern, forming a passivation layer on sidewalls of the first recess pattern and the hard mask pattern, etching a bottom surface of the first recess pattern exposed by the passivation layer to form a second recess pattern, oxidizing sidewalls of the second recess pattern to form a silicon oxide layer, removing the passivation layer and the silicon oxide layer in sequential order, and forming a gate pattern over an intended recess pattern including the first recess pattern and the second recess pattern.

A varying-width recess gate structure having a varying-width recess formed in a semiconductor device can sufficiently increase the channel length of the transistor having a gate formed in the varying-width recess, thereby effectively reducing the current leakage and improving the refresh characteristics. In the method of manufacturing the recess gate structure, etching is performed twice or more, so as to form a gate recess having varying width in the substrate, and a gate is formed in the gate recess.

Provided are a nonvolatile memory device and a method of fabricating the same in which a channel length is effectively increased and high-integration may be possible. In the nonvolatile memory device, a semiconductor device may include an active region defined by a device isolation film. The active region may include at least one projecting portion. A pair of control gate electrodes may cover both side surfaces of the at least one projecting portion, and may be spaced apart from each other. A pair of charge storage layers may be between both side surfaces of the at least one projecting portion and the pair of control gate electrodes.

Disclosed herein is a transistor for a semiconductor device and a method of forming the same. According to the present invention, a recess channel region is formed on a cell region to increase a channel length and a fin-type channel region is simultaneously formed on a peripheral circuit region to increase a channel area so as to simplify process steps, thereby improving the yield and productivity for manufacturing a semiconductor device.